riscv/rocket-chip
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update to new chisel

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This commit is contained in:
Andrew Waterman 2012-07-08 17:59:41 -07:00
parent 39d198ecdc
commit 5035374f36
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/fpu.scala
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@ -74,7 +74,7 @@ class rocketFPUDecoder extends Component
val N = Bool(false)
val Y = Bool(true)
val X = Bool(false)
val decoder = ListLookup(io.inst,
val decoder = DecodeLogic(io.inst,
List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X,X),
Array(FLW -> List(FCMD_LOAD, Y,N,N,N,N,Y,N,N,N,N,N,N,N),
FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N,N),