fix more Chisel3 deprecations

uncore/src/main/scala/broadcast.scala

@@ -48,7 +48,7 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
   trackerList.map(_.io.incoherent := io.incoherent)
 
   // Queue to store impending Put data
-  val sdq = Reg(Vec(io.iacq().data, sdqDepth))
+  val sdq = Reg(Vec(sdqDepth, io.iacq().data))
   val sdq_val = Reg(init=Bits(0, sdqDepth))
   val sdq_alloc_id = PriorityEncoder(~sdq_val)
   val sdq_rdy = !sdq_val.andR
@@ -77,7 +77,7 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
   val voluntary = io.irel().isVoluntary()
   val vwbdq_enq = io.inner.release.fire() && voluntary && io.irel().hasData()
   val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, innerDataBeats) //TODO Zero width
-  val vwbdq = Reg(Vec(io.irel().data, innerDataBeats)) //TODO Assumes nReleaseTransactors == 1
+  val vwbdq = Reg(Vec(innerDataBeats, io.irel().data)) //TODO Assumes nReleaseTransactors == 1
   when(vwbdq_enq) { vwbdq(rel_data_cnt) := io.irel().data }
 
   // Handle releases, which might be voluntary and might have data
@@ -218,7 +218,7 @@ class BroadcastAcquireTracker(trackerId: Int)
   val xact = Reg(new BufferedAcquireFromSrc()(p.alterPartial({ case TLId => innerTLId })))
   val coh = ManagerMetadata.onReset
 
-  assert(!(state != s_idle && xact.isBuiltInType() && 
+  assert(!(state =/= s_idle && xact.isBuiltInType() && 
       Vec(Acquire.putAtomicType, Acquire.getPrefetchType, Acquire.putPrefetchType).contains(xact.a_type)),
     "Broadcast Hub does not support PutAtomics or prefetches") // TODO
 
@@ -243,7 +243,7 @@ class BroadcastAcquireTracker(trackerId: Int)
   val subblock_type = xact.isSubBlockType()
 
   io.has_acquire_conflict := xact.conflicts(io.iacq()) && 
-                              (state != s_idle) &&
+                              (state =/= s_idle) &&
                               !collect_iacq_data
   io.has_acquire_match := xact.conflicts(io.iacq()) &&
                               collect_iacq_data
@@ -302,16 +302,16 @@ class BroadcastAcquireTracker(trackerId: Int)
   io.inner.release.ready := Bool(false)
   io.inner.finish.ready := Bool(false)
 
-  assert(!(state != s_idle && collect_iacq_data && io.inner.acquire.fire() &&
+  assert(!(state =/= s_idle && collect_iacq_data && io.inner.acquire.fire() &&
-    io.iacq().client_id != xact.client_id),
+    io.iacq().client_id =/= xact.client_id),
     "AcquireTracker accepted data beat from different network source than initial request.")
 
-  assert(!(state != s_idle && collect_iacq_data && io.inner.acquire.fire() &&
+  assert(!(state =/= s_idle && collect_iacq_data && io.inner.acquire.fire() &&
-    io.iacq().client_xact_id != xact.client_xact_id),
+    io.iacq().client_xact_id =/= xact.client_xact_id),
     "AcquireTracker accepted data beat from different client transaction than initial request.")
 
   assert(!(state === s_idle && io.inner.acquire.fire() &&
-    io.iacq().hasMultibeatData() && io.iacq().addr_beat != UInt(0)),
+    io.iacq().hasMultibeatData() && io.iacq().addr_beat =/= UInt(0)),
     "AcquireTracker initialized with a tail data beat.")
 
   when(collect_iacq_data) {

uncore/src/main/scala/cache.scala

@@ -102,7 +102,7 @@ class PseudoLRU(n: Int)
 }
 
 class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
-  val state = SeqMem(Bits(width = n_ways-1), n_sets)
+  val state = SeqMem(n_sets, Bits(width = n_ways-1))
   val logic = new PseudoLRU(n_ways)
   val current_state = Wire(Bits())
   val plru_way = logic.get_replace_way(current_state)
@@ -141,7 +141,7 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
   val io = new Bundle {
     val read = Decoupled(new MetaReadReq).flip
     val write = Decoupled(new MetaWriteReq(rstVal)).flip
-    val resp = Vec(rstVal.cloneType, nWays).asOutput
+    val resp = Vec(nWays, rstVal.cloneType).asOutput
   }
   val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
   val rst = rst_cnt < UInt(nSets)
@@ -151,7 +151,7 @@ class MetadataArray[T <: Metadata](onReset: () => T)(implicit p: Parameters) ext
   when (rst) { rst_cnt := rst_cnt+UInt(1) }
 
   val metabits = rstVal.getWidth
-  val tag_arr = SeqMem(Vec(UInt(width = metabits), nWays), nSets)
+  val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
   when (rst || io.write.valid) {
     tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
   }
@@ -333,7 +333,7 @@ class L2DataRWIO(implicit p: Parameters) extends L2HellaCacheBundle()(p)
 class L2DataArray(delay: Int)(implicit p: Parameters) extends L2HellaCacheModule()(p) {
   val io = new L2DataRWIO().flip
 
-  val array = SeqMem(Vec(Bits(width=8), rowBits/8), nWays*nSets*refillCycles)
+  val array = SeqMem(nWays*nSets*refillCycles, Vec(rowBits/8, Bits(width=8)))
   val ren = !io.write.valid && io.read.valid
   val raddr = Cat(OHToUInt(io.read.bits.way_en), io.read.bits.addr_idx, io.read.bits.addr_beat)
   val waddr = Cat(OHToUInt(io.write.bits.way_en), io.write.bits.addr_idx, io.write.bits.addr_beat)
@@ -449,9 +449,9 @@ abstract class L2XactTracker(implicit p: Parameters) extends XactTracker()(p)
   class CacheBlockBuffer { // TODO
     val buffer = Reg(Bits(width = p(CacheBlockBytes)*8))
 
-    def internal = Vec(Bits(width = rowBits), internalDataBeats).fromBits(buffer)
+    def internal = Vec(internalDataBeats, Bits(width = rowBits)).fromBits(buffer)
-    def inner = Vec(Bits(width = innerDataBits), innerDataBeats).fromBits(buffer)
+    def inner = Vec(innerDataBeats, Bits(width = innerDataBits)).fromBits(buffer)
-    def outer = Vec(Bits(width = outerDataBits), outerDataBeats).fromBits(buffer)
+    def outer = Vec(outerDataBeats, Bits(width = outerDataBits)).fromBits(buffer)
   }
 
   def connectDataBeatCounter[S <: L2HellaCacheBundle](inc: Bool, data: S, beat: UInt, full_block: Bool) = {
@@ -684,7 +684,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
 
   // Utility function for updating the metadata that will be kept in this cache
   def updatePendingCohWhen(flag: Bool, next: HierarchicalMetadata) {
-    when(flag && pending_coh != next) {
+    when(flag && pending_coh =/= next) {
       pending_meta_write := Bool(true)
       pending_coh := next
     }
@@ -982,7 +982,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
                              coh.inner.requiresProbesOnVoluntaryWriteback())
     val needs_inner_probes = tag_match && coh.inner.requiresProbes(xact)
     val should_update_meta = !tag_match && xact_allocate ||
-                             is_hit && pending_coh_on_hit != coh
+                             is_hit && pending_coh_on_hit =/= coh
     // Determine any changes to the coherence metadata
     when (should_update_meta) { pending_meta_write := Bool(true) }
     pending_coh := Mux(is_hit, pending_coh_on_hit, Mux(tag_match, coh, pending_coh_on_miss))

uncore/src/main/scala/coherence.scala

@@ -139,7 +139,7 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
   def clientStatesWithWritePermission = Vec(clientValid)
   def clientStatesWithDirtyData = Vec(clientValid)
 
-  def isValid (meta: ClientMetadata): Bool = meta.state != clientInvalid
+  def isValid (meta: ClientMetadata): Bool = meta.state =/= clientInvalid
 
   def getAcquireType(cmd: UInt, meta: ClientMetadata): UInt = acquireExclusive
 
@@ -230,7 +230,7 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
   def clientStatesWithWritePermission = Vec(clientExclusiveClean, clientExclusiveDirty)
   def clientStatesWithDirtyData = Vec(clientExclusiveDirty)
 
-  def isValid (meta: ClientMetadata) = meta.state != clientInvalid
+  def isValid (meta: ClientMetadata) = meta.state =/= clientInvalid
 
   def getAcquireType(cmd: UInt, meta: ClientMetadata): UInt =
     Mux(isWriteIntent(cmd), acquireExclusiveDirty, acquireExclusiveClean)
@@ -332,7 +332,7 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
   def clientStatesWithWritePermission = Vec(clientExclusiveDirty)
   def clientStatesWithDirtyData = Vec(clientExclusiveDirty)
 
-  def isValid(meta: ClientMetadata): Bool = meta.state != clientInvalid
+  def isValid(meta: ClientMetadata): Bool = meta.state =/= clientInvalid
 
   def getAcquireType(cmd: UInt, meta: ClientMetadata): UInt =
     Mux(isWriteIntent(cmd), acquireExclusive, acquireShared)
@@ -385,7 +385,7 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
   def requiresProbes(a: HasAcquireType, meta: ManagerMetadata) =
     Mux(dir.none(meta.sharers), Bool(false), 
       Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive
-        Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared)))
+        Mux(a.isBuiltInType(), a.hasData(), a.a_type =/= acquireShared)))
 
   def requiresProbes(cmd: UInt, meta: ManagerMetadata) = !dir.none(meta.sharers)
 
@@ -450,7 +450,7 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
   def clientStatesWithWritePermission = Vec(clientExclusiveClean, clientExclusiveDirty)
   def clientStatesWithDirtyData = Vec(clientExclusiveDirty)
 
-  def isValid(meta: ClientMetadata): Bool = meta.state != clientInvalid
+  def isValid(meta: ClientMetadata): Bool = meta.state =/= clientInvalid
 
   def getAcquireType(cmd: UInt, meta: ClientMetadata): UInt =
     Mux(isWriteIntent(cmd), acquireExclusive, acquireShared)
@@ -505,7 +505,7 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
   def requiresProbes(a: HasAcquireType, meta: ManagerMetadata) =
     Mux(dir.none(meta.sharers), Bool(false), 
       Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive
-        Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared)))
+        Mux(a.isBuiltInType(), a.hasData(), a.a_type =/= acquireShared)))
 
   def requiresProbes(cmd: UInt, meta: ManagerMetadata) = !dir.none(meta.sharers)
 
@@ -566,7 +566,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
   def clientStatesWithWritePermission = Vec(clientExclusiveClean, clientExclusiveDirty, clientMigratoryClean, clientMigratoryDirty)
   def clientStatesWithDirtyData = Vec(clientExclusiveDirty, clientMigratoryDirty)
 
-  def isValid (meta: ClientMetadata): Bool = meta.state != clientInvalid
+  def isValid (meta: ClientMetadata): Bool = meta.state =/= clientInvalid
 
   def getAcquireType(cmd: UInt, meta: ClientMetadata): UInt =
     Mux(isWriteIntent(cmd), 
@@ -594,7 +594,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
                            releaseInvalidateAckMigratory, releaseInvalidateAck),
       probeInvalidateOthers -> Mux(clientSharedByTwo === meta.state,
                                  releaseInvalidateAckMigratory, releaseInvalidateAck),
-      probeDowngrade  -> Mux(meta.state != clientInvalid,
+      probeDowngrade  -> Mux(meta.state =/= clientInvalid,
                            releaseDowngradeAckHasCopy, releaseDowngradeAck),
       probeCopy       -> releaseCopyAck))
     Mux(dirty, with_data, without_data)
@@ -646,7 +646,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
   def requiresProbes(a: HasAcquireType, meta: ManagerMetadata) =
     Mux(dir.none(meta.sharers), Bool(false),
       Mux(dir.one(meta.sharers), Bool(true), //TODO: for now we assume it's Exclusive
-        Mux(a.isBuiltInType(), a.hasData(), a.a_type != acquireShared)))
+        Mux(a.isBuiltInType(), a.hasData(), a.a_type =/= acquireShared)))
 
   def requiresProbes(cmd: UInt, meta: ManagerMetadata) = !dir.none(meta.sharers)
 

uncore/src/main/scala/htif.scala

@@ -49,7 +49,7 @@ class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
 class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHtifParameters {
   val io = new Bundle {
     val host = new HostIO(w)
-    val cpu = Vec(new HtifIO, nCores).flip
+    val cpu = Vec(nCores, new HtifIO).flip
     val mem = new ClientUncachedTileLinkIO
     val scr = new SmiIO(scrDataBits, scrAddrBits)
   }
@@ -99,7 +99,7 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
 
   val bad_mem_packet = size(offsetBits-1-3,0).orR || addr(offsetBits-1-3,0).orR
   val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, bad_mem_packet,
-             Mux(cmd === cmd_readcr || cmd === cmd_writecr, size != UInt(1),
+             Mux(cmd === cmd_readcr || cmd === cmd_writecr, size =/= UInt(1),
              Bool(true)))
 
   val tx_count = Reg(init=UInt(0, rx_count_w))
@@ -110,7 +110,7 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
     tx_count := tx_count + UInt(1)
   }
 
-  val rx_done = rx_word_done && Mux(rx_word_count === UInt(0), next_cmd != cmd_writemem && next_cmd != cmd_writecr, rx_word_count === size || rx_word_count(log2Up(packet_ram_depth)-1,0) === UInt(0))
+  val rx_done = rx_word_done && Mux(rx_word_count === UInt(0), next_cmd =/= cmd_writemem && next_cmd =/= cmd_writecr, rx_word_count === size || rx_word_count(log2Up(packet_ram_depth)-1,0) === UInt(0))
   val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr || cmd === cmd_writecr), size, UInt(0))
   val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UInt(0) && packet_ram_raddr.andR)
 
@@ -147,7 +147,7 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
       rx_count := UInt(0)
       tx_count := UInt(0)
     }
-    state := Mux(cmd === cmd_readmem && pos != UInt(0), state_mem_rreq, state_rx)
+    state := Mux(cmd === cmd_readmem && pos =/= UInt(0), state_mem_rreq, state_rx)
   }
 
   val n = dataBits/short_request_bits
@@ -177,7 +177,7 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
 
     val cpu = io.cpu(i)
     val me = csr_coreid === UInt(i)
-    cpu.csr.req.valid := state === state_csr_req && me && csr_addr != UInt(csr_RESET)
+    cpu.csr.req.valid := state === state_csr_req && me && csr_addr =/= UInt(csr_RESET)
     cpu.csr.req.bits.rw := cmd === cmd_writecr
     cpu.csr.req.bits.addr := csr_addr
     cpu.csr.req.bits.data := csr_wdata

uncore/src/main/scala/metadata.scala

@@ -20,7 +20,7 @@ class ClientMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
 
   /** Metadata equality */
   def ===(rhs: ClientMetadata): Bool = this.state === rhs.state
-  def !=(rhs: ClientMetadata): Bool = !this.===(rhs)
+  def =/=(rhs: ClientMetadata): Bool = !this.===(rhs)
 
   /** Is the block's data present in this cache */
   def isValid(dummy: Int = 0): Bool = co.isValid(this)
@@ -168,7 +168,7 @@ class ManagerMetadata(implicit p: Parameters) extends CoherenceMetadata()(p) {
   /** Metadata equality */
   def ===(rhs: ManagerMetadata): Bool = //this.state === rhs.state && TODO: Fix 0-width wires in Chisel
                                          this.sharers === rhs.sharers
-  def !=(rhs: ManagerMetadata): Bool = !this.===(rhs)
+  def =/=(rhs: ManagerMetadata): Bool = !this.===(rhs)
 
   /** Converts the directory info into an N-hot sharer bitvector (i.e. full representation) */
   def full(dummy: Int = 0): UInt = co.dir.full(this.sharers)
@@ -319,7 +319,7 @@ class HierarchicalMetadata(implicit p: Parameters) extends CoherenceMetadata()(p
   val outer: ClientMetadata = new ClientMetadata()(p.alterPartial({case TLId => p(OuterTLId)}))
   def ===(rhs: HierarchicalMetadata): Bool = 
     this.inner === rhs.inner && this.outer === rhs.outer
-  def !=(rhs: HierarchicalMetadata): Bool = !this.===(rhs)
+  def =/=(rhs: HierarchicalMetadata): Bool = !this.===(rhs)
 }
 
 /** Factories for HierarchicalMetadata, including on reset */

uncore/src/main/scala/network.scala

@@ -19,8 +19,8 @@ class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle {
 }
 
 class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle {
-    val in  = Vec(Decoupled(new PhysicalNetworkIO(n,dType)), n).flip 
+    val in  = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType))).flip 
-    val out = Vec(Decoupled(new PhysicalNetworkIO(n,dType)), n)
+    val out = Vec(n, Decoupled(new PhysicalNetworkIO(n,dType)))
 }
 
 abstract class PhysicalNetwork extends Module

uncore/src/main/scala/scr.scala

@@ -5,7 +5,7 @@ import junctions.{SmiIO, MMIOBase}
 import cde.Parameters
 
 class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
-  val rdata = Vec(Bits(INPUT, scrDataBits), nSCR)
+  val rdata = Vec(nSCR, Bits(INPUT, scrDataBits))
   val wen = Bool(OUTPUT)
   val waddr = UInt(OUTPUT, log2Up(nSCR))
   val wdata = Bits(OUTPUT, scrDataBits)
@@ -17,7 +17,7 @@ class SCRFile(implicit p: Parameters) extends HtifModule()(p) {
     val scr = new SCRIO
   }
 
-  val scr_rdata = Wire(Vec(Bits(width=scrDataBits), io.scr.rdata.size))
+  val scr_rdata = Wire(Vec(io.scr.rdata.size, Bits(width=scrDataBits)))
   for (i <- 0 until scr_rdata.size)
     scr_rdata(i) := io.scr.rdata(i)
   scr_rdata(0) := UInt(nCores)

uncore/src/main/scala/tilelink.scala

@@ -1058,7 +1058,7 @@ trait TileLinkArbiterLike extends HasTileLinkParameters {
 abstract class UncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module
     with TileLinkArbiterLike {
   val io = new Bundle {
-    val in = Vec(new UncachedTileLinkIO, arbN).flip
+    val in = Vec(arbN, new UncachedTileLinkIO).flip
     val out = new UncachedTileLinkIO
   }
   hookupClientSource(io.in.map(_.acquire), io.out.acquire)
@@ -1070,7 +1070,7 @@ abstract class UncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Paramete
 abstract class TileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module
     with TileLinkArbiterLike {
   val io = new Bundle {
-    val in = Vec(new TileLinkIO, arbN).flip
+    val in = Vec(arbN, new TileLinkIO).flip
     val out = new TileLinkIO
   }
   hookupClientSource(io.in.map(_.acquire), io.out.acquire)
@@ -1114,7 +1114,7 @@ class TileLinkIOArbiterThatUsesNewId(val n: Int)(implicit p: Parameters) extends
 /** Concrete uncached client-side arbiter that appends the arbiter's port id to client_xact_id */
 class ClientUncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module with TileLinkArbiterLike with AppendsArbiterId {
   val io = new Bundle {
-    val in = Vec(new ClientUncachedTileLinkIO, arbN).flip
+    val in = Vec(arbN, new ClientUncachedTileLinkIO).flip
     val out = new ClientUncachedTileLinkIO
   }
   hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
@@ -1124,7 +1124,7 @@ class ClientUncachedTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters)
 /** Concrete client-side arbiter that appends the arbiter's port id to client_xact_id */
 class ClientTileLinkIOArbiter(val arbN: Int)(implicit val p: Parameters) extends Module with TileLinkArbiterLike with AppendsArbiterId {
   val io = new Bundle {
-    val in = Vec(new ClientTileLinkIO, arbN).flip
+    val in = Vec(arbN, new ClientTileLinkIO).flip
     val out = new ClientTileLinkIO
   }
   hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)

uncore/src/main/scala/uncore.scala

@@ -62,7 +62,7 @@ trait HasCoherenceAgentWiringHelpers {
 
 trait HasInnerTLIO extends HasCoherenceAgentParameters {
   val inner = new ManagerTileLinkIO()(p.alterPartial({case TLId => p(InnerTLId)}))
-  val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput
+  val incoherent = Vec(inner.tlNCachingClients, Bool()).asInput
   def iacq(dummy: Int = 0) = inner.acquire.bits
   def iprb(dummy: Int = 0) = inner.probe.bits
   def irel(dummy: Int = 0) = inner.release.bits

uncore/src/main/scala/util.scala

@@ -75,7 +75,7 @@ class FlowThroughSerializer[T <: Bundle with HasTileLinkData](gen: T, n: Int) ex
     val rbits = Reg{io.in.bits}
     val active = Reg(init=Bool(false))
 
-    val shifter = Vec(Bits(width = narrowWidth), n)
+    val shifter = Vec(n, Bits(width = narrowWidth))
     (0 until n).foreach { 
       i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth)
     }
@@ -138,8 +138,8 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
     }
   }
 
-  val roq_data = Reg(Vec(dType.cloneType, size))
+  val roq_data = Reg(Vec(size, dType.cloneType))
-  val roq_tags = Reg(Vec(UInt(width = tagWidth), size))
+  val roq_tags = Reg(Vec(size, UInt(width = tagWidth)))
   val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
 
   val roq_enq_addr = PriorityEncoder(roq_free)