riscv/rocket-chip
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fix more Chisel3 deprecations

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Howard Mao
2016-01-14 13:47:47 -08:00
parent 0b90b8fe5f
commit 4ff1aea288
10 changed files with 47 additions and 47 deletions
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uncore/src/main/scala/uncore.scala
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@ -62,7 +62,7 @@ trait HasCoherenceAgentWiringHelpers {
trait HasInnerTLIO extends HasCoherenceAgentParameters {
val inner = new ManagerTileLinkIO()(p.alterPartial({case TLId => p(InnerTLId)}))
val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput
val incoherent = Vec(inner.tlNCachingClients, Bool()).asInput
def iacq(dummy: Int = 0) = inner.acquire.bits
def iprb(dummy: Int = 0) = inner.probe.bits
def irel(dummy: Int = 0) = inner.release.bits