riscv/rocket-chip
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fix more Chisel3 deprecations

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Howard Mao
2016-01-14 13:47:47 -08:00
parent 0b90b8fe5f
commit 4ff1aea288
10 changed files with 47 additions and 47 deletions
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4
uncore/src/main/scala/scr.scala
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@@ -5,7 +5,7 @@ import junctions.{SmiIO, MMIOBase}
import cde.Parameters
class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
val rdata = Vec(Bits(INPUT, scrDataBits), nSCR)
val rdata = Vec(nSCR, Bits(INPUT, scrDataBits))
val wen = Bool(OUTPUT)
val waddr = UInt(OUTPUT, log2Up(nSCR))
val wdata = Bits(OUTPUT, scrDataBits)
@@ -17,7 +17,7 @@ class SCRFile(implicit p: Parameters) extends HtifModule()(p) {
val scr = new SCRIO
}
val scr_rdata = Wire(Vec(Bits(width=scrDataBits), io.scr.rdata.size))
val scr_rdata = Wire(Vec(io.scr.rdata.size, Bits(width=scrDataBits)))
for (i <- 0 until scr_rdata.size)
scr_rdata(i) := io.scr.rdata(i)
scr_rdata(0) := UInt(nCores)