riscv/rocket-chip
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Merge pull request #518 from ucb-bar/dtm_regression

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jtag_dtm: Update regression to run and pass.
This commit is contained in:
Megan Wachs 2017-01-18 14:39:53 -08:00 committed by GitHub
commit 4fe75965a0
3 changed files with 12 additions and 7 deletions
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7
regression/Makefile
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@ -218,9 +218,10 @@ stamps/%/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/%/emulator-debug.stamp
# Targets for JTAG DTM full-chain simulation # Targets for JTAG DTM full-chain simulation
OPENOCD_HEAD ?= riscv #OPENOCD_HEAD ?= riscv
OPENOCD_INSTALL ?= $(abspath $(TOP))/openocd-install OPENOCD_INSTALL ?= $(abspath $(TOP))/openocd-install
OPENOCD_VERSION = $(shell git ls-remote http://github.com/sifive/openocd.git $(OPENOCD_HEAD) | awk '{print $$1}') #OPENOCD_VERSION = $(shell git ls-remote http://github.com/sifive/openocd.git $(OPENOCD_HEAD) | awk '{print $$1}')
OPENOCD_VERSION = 193f63094891cd3fe6a5032fef2c71d09f063ff4
OPENOCD_DIR = $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/ OPENOCD_DIR = $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/
$(OPENOCD_DIR)/bin/openocd: $(OPENOCD_DIR)/bin/openocd:
@ -237,7 +238,7 @@ install_openocd: $(OPENOCD_DIR)/bin/openocd
# If this is defined empty, then all tests would run. # If this is defined empty, then all tests would run.
# Running a list of tests is not supported. # Running a list of tests is not supported.
JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0 JTAG_DTM_TEST ?= SimpleS0Test
stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp
$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \ $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \

6
src/main/scala/rocketchip/ExampleTop.scala
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@ -30,7 +30,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _
class ExampleRocketTop(implicit p: Parameters) extends ExampleTop class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
with PeripheryBootROM with PeripheryBootROM
with PeripheryDTM with PeripheryDebug
with PeripheryCounter with PeripheryCounter
with HardwiredResetVector with HardwiredResetVector
with RocketPlexMaster { with RocketPlexMaster {
@ -39,14 +39,14 @@ class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer) class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
with PeripheryBootROMBundle with PeripheryBootROMBundle
with PeripheryDTMBundle with PeripheryDebugBundle
with PeripheryCounterBundle with PeripheryCounterBundle
with HardwiredResetVectorBundle with HardwiredResetVectorBundle
with RocketPlexMasterBundle with RocketPlexMasterBundle
class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
with PeripheryBootROMModule with PeripheryBootROMModule
with PeripheryDTMModule with PeripheryDebugModule
with PeripheryCounterModule with PeripheryCounterModule
with HardwiredResetVectorModule with HardwiredResetVectorModule
with RocketPlexMasterModule with RocketPlexMasterModule

6
src/main/scala/rocketchip/TestHarness.scala
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@ -26,7 +26,11 @@ class TestHarness()(implicit p: Parameters) extends Module {
} }
} }
val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug, io.success) if (!p(IncludeJtagDTM)) {
val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug.get, io.success)
} else {
val jtag = Module(new JTAGVPI).connect(dut.io.jtag.get, reset, io.success)
}
val mmio_sim = Module(LazyModule(new SimAXIMem(4096)).module) val mmio_sim = Module(LazyModule(new SimAXIMem(4096)).module)
mmio_sim.io.axi4 <> dut.io.mmio_axi4 mmio_sim.io.axi4 <> dut.io.mmio_axi4