Add performance counter facility
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@ -35,6 +35,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val flush_icache = Bool(OUTPUT)
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val flush_tlb = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBitsExtended)
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// performance events
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val acquire = Bool(INPUT)
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}
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class Frontend(implicit p: Parameters) extends LazyModule {
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@ -150,6 +153,9 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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io.cpu.resp.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt_if
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io.cpu.resp.bits.btb.valid := s2_btb_resp_valid
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io.cpu.resp.bits.btb.bits := s2_btb_resp_bits
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// performance events
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io.cpu.acquire := icache.io.mem(0).a.fire()
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}
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/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
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