diff --git a/vsrc/AsyncResetReg.v b/vsrc/AsyncResetReg.v
index 37fb0402..4158734f 100644
--- a/vsrc/AsyncResetReg.v
+++ b/vsrc/AsyncResetReg.v
@@ -24,6 +24,19 @@
   *  
   */
 
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+
 module AsyncResetReg (
                       input      d,
                       output reg q,
@@ -32,6 +45,20 @@ module AsyncResetReg (
                       input      clk,
                       input      rst);
    
+`ifdef RANDOMIZE
+   integer                       initvar;
+   reg [31:0]                    _RAND;
+   initial begin
+ `ifndef verilator
+      #0.002 begin end
+ `endif
+ `ifdef RANDOMIZE_REG_INIT
+      _RAND = {1{$random}};
+      q = _RAND[0];
+ `endif
+   end
+`endif //  `ifdef RANDOMIZE
+   
    always @(posedge clk or posedge rst) begin
 
       if (rst) begin