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tilelink2: annotate which test generates RAMModel output

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This commit is contained in:
Wesley W. Terpstra 2017-04-13 11:51:10 -07:00
parent 0b65fe9532
commit 4f0ae1eab7
9 changed files with 14 additions and 14 deletions
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2
src/main/scala/uncore/tilelink2/AsyncCrossing.scala
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@ -138,7 +138,7 @@ class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) ext
import unittest._
class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule {
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("AsyncCrossing"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
val fuzz = LazyModule(new TLFuzzer(5000))
val cross = LazyModule(new TLAsyncCrossing)

2
src/main/scala/uncore/tilelink2/AtomicAutomata.scala
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@ -295,7 +295,7 @@ import unittest._
class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node

2
src/main/scala/uncore/tilelink2/Fragmenter.scala
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@ -264,7 +264,7 @@ import unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node

2
src/main/scala/uncore/tilelink2/HintHandler.scala
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@ -112,7 +112,7 @@ import unittest._
class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("HintHandler"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node

12
src/main/scala/uncore/tilelink2/RationalCrossing.scala
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@ -149,10 +149,10 @@ class TLRationalCrossing(direction: RationalDirection = Symmetric)(implicit p: P
/** Synthesizeable unit tests */
import unittest._
class TLRAMRationalCrossingSource(implicit p: Parameters) extends LazyModule {
class TLRAMRationalCrossingSource(name: String)(implicit p: Parameters) extends LazyModule {
val node = TLRationalOutputNode()
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel(name))
model.node := fuzz.node
node := TLRationalCrossingSource()(TLDelayer(0.25)(model.node))
@ -180,19 +180,19 @@ class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parame
}
class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule {
val sym_fast_source = LazyModule(new TLRAMRationalCrossingSource)
val sym_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_fast"))
val sym_slow_sink = LazyModule(new TLRAMRationalCrossingSink(Symmetric))
sym_slow_sink.node := sym_fast_source.node
val sym_slow_source = LazyModule(new TLRAMRationalCrossingSource)
val sym_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing sym_slow"))
val sym_fast_sink = LazyModule(new TLRAMRationalCrossingSink(Symmetric))
sym_fast_sink.node := sym_slow_source.node
val fix_fast_source = LazyModule(new TLRAMRationalCrossingSource)
val fix_fast_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing fast"))
val fix_slow_sink = LazyModule(new TLRAMRationalCrossingSink(FastToSlow))
fix_slow_sink.node := fix_fast_source.node
val fix_slow_source = LazyModule(new TLRAMRationalCrossingSource)
val fix_slow_source = LazyModule(new TLRAMRationalCrossingSource("RationalCrossing slow"))
val fix_fast_sink = LazyModule(new TLRAMRationalCrossingSink(SlowToFast))
fix_fast_sink.node := fix_slow_source.node

2
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -91,7 +91,7 @@ import unittest._
class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("SRAMSimple"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node

2
src/main/scala/uncore/tilelink2/TestRAM.scala
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@ -67,7 +67,7 @@ import unittest._
class TLRAMZeroDelay(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("ZeroDelay"))
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node

2
src/main/scala/uncore/tilelink2/WidthWidget.scala
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@ -176,7 +176,7 @@ import unittest._
class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node

2
src/main/scala/uncore/tilelink2/Xbar.scala
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@ -215,7 +215,7 @@ import unittest._
class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
model.node := fuzz.node