From 4efcb5a1390700f70b2140106ddd521576b9d4c1 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 3 May 2017 07:54:46 -0700 Subject: [PATCH] Increase frontend decoupling (#722) Reduce pathological RVC stalls --- src/main/scala/rocket/Frontend.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index f4d5ff78..c2f69fd7 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -69,9 +69,9 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) val icache = outer.icache.module val tlb = Module(new TLB(log2Ceil(coreInstBytes*fetchWidth), nTLBEntries)) - val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 3, flow = true)) } + val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 4, flow = true)) } - val s0_valid = io.cpu.req.valid || fq.io.enq.ready + val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-2) val s1_pc = Reg(UInt(width=vaddrBitsExtended)) val s1_speculative = Reg(Bool()) val s2_valid = Reg(init=Bool(true))