riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

RegisterRouter: support devices with gaps

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-03-20 14:48:51 -07:00
parent 431cb41e27
commit 4eef317e84
3 changed files with 13 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/devices/Clint.scala
View File

@ -40,7 +40,7 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Paramet
} }
val node = TLRegisterNode( val node = TLRegisterNode(
address = AddressSet(address, size-1), address = Seq(AddressSet(address, size-1)),
device = device, device = device,
beatBytes = p(XLen)/8) beatBytes = p(XLen)/8)

2
src/main/scala/uncore/devices/Plic.scala
View File

@ -72,7 +72,7 @@ class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parame
} }
val node = TLRegisterNode( val node = TLRegisterNode(
address = AddressSet(address, PLICConsts.size-1), address = Seq(AddressSet(address, PLICConsts.size-1)),
device = device, device = device,
beatBytes = p(XLen)/8, beatBytes = p(XLen)/8,
undefZero = false) undefZero = false)

17
src/main/scala/uncore/tilelink2/RegisterRouter.scala
View File

@ -9,7 +9,7 @@ import regmapper._
import scala.math.{min,max} import scala.math.{min,max}
class TLRegisterNode( class TLRegisterNode(
address: AddressSet, address: Seq[AddressSet],
device: Device, device: Device,
deviceKey: String = "reg", deviceKey: String = "reg",
concurrency: Int = 0, concurrency: Int = 0,
@ -18,7 +18,7 @@ class TLRegisterNode(
executable: Boolean = false) executable: Boolean = false)
extends TLManagerNode(Seq(TLManagerPortParameters( extends TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters( Seq(TLManagerParameters(
address = Seq(address), address = address,
resources = Seq(Resource(device, deviceKey)), resources = Seq(Resource(device, deviceKey)),
executable = executable, executable = executable,
supportsGet = TransferSizes(1, beatBytes), supportsGet = TransferSizes(1, beatBytes),
@ -28,7 +28,12 @@ class TLRegisterNode(
beatBytes = beatBytes, beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) // the Queue adds at most one cycle minLatency = min(concurrency, 1)))) // the Queue adds at most one cycle
{ {
require (address.contiguous) val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be // Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields. // configured to route all requests to the listed RegFields.
@ -43,7 +48,7 @@ class TLRegisterNode(
val (sourceEnd, sourceOff) = (edge.bundle.sourceBits + sizeEnd, sizeEnd) val (sourceEnd, sourceOff) = (edge.bundle.sourceBits + sizeEnd, sizeEnd)
val (addrLoEnd, addrLoOff) = (log2Up(beatBytes) + sourceEnd, sourceEnd) val (addrLoEnd, addrLoOff) = (log2Up(beatBytes) + sourceEnd, sourceEnd)
val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, addrLoEnd) val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, addrLoEnd)
val in = Wire(Decoupled(new RegMapperInput(params))) val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits) in.bits.index := edge.addr_hi(a.bits)
@ -81,7 +86,7 @@ class TLRegisterNode(
object TLRegisterNode object TLRegisterNode
{ {
def apply( def apply(
address: AddressSet, address: Seq[AddressSet],
device: Device, device: Device,
deviceKey: String = "reg", deviceKey: String = "reg",
concurrency: Int = 0, concurrency: Int = 0,
@ -98,7 +103,7 @@ object TLRegisterNode
abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{ {
val device = new SimpleDevice(devname, devcompat) val device = new SimpleDevice(devname, devcompat)
val node = TLRegisterNode(address, device, "reg", concurrency, beatBytes, undefZero, executable) val node = TLRegisterNode(Seq(address), device, "reg", concurrency, beatBytes, undefZero, executable)
val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int")))) val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int"))))
} }