riscv/rocket-chip
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Provide option to support AMOs only on I/O, not DTIM/D$

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This commit is contained in:
Andrew Waterman 2017-11-09 17:25:10 -08:00
parent efdb418559
commit 4ebca73d59
5 changed files with 11 additions and 7 deletions
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6
src/main/scala/rocket/DCache.scala
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@ -76,7 +76,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val eccBits = eccBytes * 8 val eccBits = eccBytes * 8
require(isPow2(eccBytes) && eccBytes <= wordBytes) require(isPow2(eccBytes) && eccBytes <= wordBytes)
require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode]) require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode])
val usingRMW = eccBytes > 1 || usingAtomics val usingRMW = eccBytes > 1 || usingAtomicsInCache
// tags // tags
val replacer = cacheParams.replacement val replacer = cacheParams.replacement
@ -688,11 +688,11 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
if (usingRMW) { if (usingRMW) {
val amoalu = Module(new AMOALU(xLen)) val amoalu = Module(new AMOALU(xLen))
amoalu.io.mask := pstore1_mask amoalu.io.mask := pstore1_mask
amoalu.io.cmd := (if (usingAtomics) pstore1_cmd else M_XWR) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR)
amoalu.io.lhs := s2_data_word amoalu.io.lhs := s2_data_word
amoalu.io.rhs := pstore1_data amoalu.io.rhs := pstore1_data
pstore1_storegen_data := amoalu.io.out pstore1_storegen_data := amoalu.io.out
} else { } else if (!usingAtomics) {
assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation")
} }
when (s2_correct) { pstore1_storegen_data := s2_data_word_corrected } when (s2_correct) { pstore1_storegen_data := s2_data_word_corrected }

1
src/main/scala/rocket/RocketCore.scala
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@ -18,6 +18,7 @@ case class RocketCoreParams(
useUser: Boolean = false, useUser: Boolean = false,
useDebug: Boolean = true, useDebug: Boolean = true,
useAtomics: Boolean = true, useAtomics: Boolean = true,
useAtomicsOnlyForIO: Boolean = false,
useCompressed: Boolean = true, useCompressed: Boolean = true,
nLocalInterrupts: Int = 0, nLocalInterrupts: Int = 0,
nBreakpoints: Int = 1, nBreakpoints: Int = 1,

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -100,7 +100,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val cacheBlockBytes = p(CacheBlockBytes) val cacheBlockBytes = p(CacheBlockBytes)
val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s => val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics))) LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)))
} }
val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntIdentityNode()) val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntIdentityNode())

6
src/main/scala/rocket/TLB.scala
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@ -117,8 +117,8 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous
val prot_r = fastCheck(_.supportsGet) && pmp.io.r val prot_r = fastCheck(_.supportsGet) && pmp.io.r
val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w
val prot_al = fastCheck(_.supportsLogical) || cacheable val prot_al = fastCheck(_.supportsLogical) || (cacheable && usingAtomicsInCache)
val prot_aa = fastCheck(_.supportsArithmetic) || cacheable val prot_aa = fastCheck(_.supportsArithmetic) || (cacheable && usingAtomicsInCache)
val prot_x = fastCheck(_.executable) && pmp.io.x val prot_x = fastCheck(_.executable) && pmp.io.x
val prot_eff = fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType) val prot_eff = fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
@ -190,7 +190,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TL
(if (vpnBits == vpnBitsExtended) Bool(false) (if (vpnBits == vpnBitsExtended) Bool(false)
else (io.req.bits.vaddr.asSInt < 0.S) =/= (vpn.asSInt < 0.S)) else (io.req.bits.vaddr.asSInt < 0.S) =/= (vpn.asSInt < 0.S))
val lrscAllowed = Mux(Bool(usingDataScratchpad), 0.U, c_array) val lrscAllowed = Mux(Bool(usingDataScratchpad || usingAtomicsOnlyForIO), 0.U, c_array)
val ae_array = val ae_array =
Mux(misaligned, eff_array, 0.U) | Mux(misaligned, eff_array, 0.U) |
Mux(Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC), ~lrscAllowed, 0.U) Mux(Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC), ~lrscAllowed, 0.U)

3
src/main/scala/tile/Core.scala
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@ -17,6 +17,7 @@ trait CoreParams {
val useUser: Boolean val useUser: Boolean
val useDebug: Boolean val useDebug: Boolean
val useAtomics: Boolean val useAtomics: Boolean
val useAtomicsOnlyForIO: Boolean
val useCompressed: Boolean val useCompressed: Boolean
val mulDiv: Option[MulDivParams] val mulDiv: Option[MulDivParams]
val fpu: Option[FPUParams] val fpu: Option[FPUParams]
@ -47,6 +48,8 @@ trait HasCoreParameters extends HasTileParameters {
val usingMulDiv = coreParams.mulDiv.nonEmpty val usingMulDiv = coreParams.mulDiv.nonEmpty
val usingFPU = coreParams.fpu.nonEmpty val usingFPU = coreParams.fpu.nonEmpty
val usingAtomics = coreParams.useAtomics val usingAtomics = coreParams.useAtomics
val usingAtomicsOnlyForIO = coreParams.useAtomicsOnlyForIO
val usingAtomicsInCache = usingAtomics && !usingAtomicsOnlyForIO
val usingCompressed = coreParams.useCompressed val usingCompressed = coreParams.useCompressed
val retireWidth = coreParams.retireWidth val retireWidth = coreParams.retireWidth