riscv/rocket-chip
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Provide option to support AMOs only on I/O, not DTIM/D$

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This commit is contained in:
Andrew Waterman
2017-11-09 17:25:10 -08:00
parent efdb418559
commit 4ebca73d59
5 changed files with 11 additions and 7 deletions
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6
src/main/scala/rocket/DCache.scala
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@ -76,7 +76,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val eccBits = eccBytes * 8
require(isPow2(eccBytes) && eccBytes <= wordBytes)
require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode])
val usingRMW = eccBytes > 1 || usingAtomics
val usingRMW = eccBytes > 1 || usingAtomicsInCache
// tags
val replacer = cacheParams.replacement
@ -688,11 +688,11 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
if (usingRMW) {
val amoalu = Module(new AMOALU(xLen))
amoalu.io.mask := pstore1_mask
amoalu.io.cmd := (if (usingAtomics) pstore1_cmd else M_XWR)
amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR)
amoalu.io.lhs := s2_data_word
amoalu.io.rhs := pstore1_data
pstore1_storegen_data := amoalu.io.out
} else {
} else if (!usingAtomics) {
assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation")
}
when (s2_correct) { pstore1_storegen_data := s2_data_word_corrected }