riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Simplify logic further and bugfix

Browse Source 
complete was being set unconditionally
This commit is contained in:
Wesley W. Terpstra 2017-06-30 10:07:39 -07:00 committed by GitHub
parent e8e709c941
commit 4e9f65b2ef
1 changed files with 3 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/main/scala/uncore/devices/Plic.scala
View File

@ -197,12 +197,9 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
// a time through the TL interface
// (Note -- PLIC doesn't care which hart writes the register)
val completer = Wire(Vec(nHarts, Bool()))
val completingDevs = Wire(Vec(nHarts, UInt(width = log2Up(pending.size))))
val completing = Vec.tabulate(nHarts){i => Mux(completer(i), UIntToOH(completingDevs(i), nDevices+1), UInt(0))}
val completedDevs = Vec(completing.reduceLeft( _ | _ ).toBools)
(gateways zip completedDevs) foreach { case (g, c) =>
g.complete := c
val irq = data.extract(log2Ceil(nDevices+1)-1, 0)
when (completer.reduce(_ || _)) {
gateways(irq).complete := Bool(false)
}
val hartRegFields = Seq.tabulate(nHarts) { i =>
@ -214,8 +211,6 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
(Bool(true), maxDevs(i))
},
RegWriteFn { (valid, data) =>
val irq = data.extract(log2Ceil(nDevices+1)-1, 0)
completingDevs(i) := irq
completer(i) := valid && enables(i)(irq)
Bool(true)
}