Simplify logic further and bugfix
complete was being set unconditionally
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@ -197,12 +197,9 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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// a time through the TL interface
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// a time through the TL interface
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// (Note -- PLIC doesn't care which hart writes the register)
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// (Note -- PLIC doesn't care which hart writes the register)
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val completer = Wire(Vec(nHarts, Bool()))
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val completer = Wire(Vec(nHarts, Bool()))
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val completingDevs = Wire(Vec(nHarts, UInt(width = log2Up(pending.size))))
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val irq = data.extract(log2Ceil(nDevices+1)-1, 0)
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val completing = Vec.tabulate(nHarts){i => Mux(completer(i), UIntToOH(completingDevs(i), nDevices+1), UInt(0))}
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when (completer.reduce(_ || _)) {
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val completedDevs = Vec(completing.reduceLeft( _ | _ ).toBools)
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gateways(irq).complete := Bool(false)
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(gateways zip completedDevs) foreach { case (g, c) =>
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g.complete := c
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}
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}
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val hartRegFields = Seq.tabulate(nHarts) { i =>
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val hartRegFields = Seq.tabulate(nHarts) { i =>
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@ -214,8 +211,6 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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(Bool(true), maxDevs(i))
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(Bool(true), maxDevs(i))
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},
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},
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RegWriteFn { (valid, data) =>
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RegWriteFn { (valid, data) =>
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val irq = data.extract(log2Ceil(nDevices+1)-1, 0)
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completingDevs(i) := irq
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completer(i) := valid && enables(i)(irq)
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completer(i) := valid && enables(i)(irq)
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Bool(true)
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Bool(true)
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}
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}
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