From 4e40f9bb597a2d5931fba33b6e32b0525c33f599 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 13 Oct 2016 10:29:55 -0700
Subject: [PATCH] tilelink2 Nodes: appease the PC police

---
 src/main/scala/regmapper/RegMapper.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/regmapper/RegMapper.scala b/src/main/scala/regmapper/RegMapper.scala
index f456b899..57bf7f82 100644
--- a/src/main/scala/regmapper/RegMapper.scala
+++ b/src/main/scala/regmapper/RegMapper.scala
@@ -31,7 +31,7 @@ object RegMapper
   // Create a generic register-based device
   def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*) = {
     val bytemap = mapping.toList
-    // Don't be an asshole...
+    // Negative addresses are bad
     bytemap.foreach { byte => require (byte._1 >= 0) }
 
     // Transform all fields into bit offsets Seq[(bit, field)]