riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into ipxact_descs

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This commit is contained in:
Megan Wachs 2018-03-13 09:26:47 -07:00
commit 4e11491531
1 changed files with 3 additions and 4 deletions
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7
src/main/scala/devices/debug/Debug.scala
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@ -785,7 +785,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
val go = Bool()
}
val flags = Wire(init = Vec.fill(nComponents){new flagBundle().fromBits(0.U)})
val flags = Wire(init = Vec.fill(1024){new flagBundle().fromBits(0.U)})
assert ((cfg.hartSelToHartId(selectedHartReg) < 1024.U),
"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < 1024 for it to work.");
flags(cfg.hartSelToHartId(selectedHartReg)).go := goReg
@ -905,10 +905,9 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"),
abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}),
FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"),
flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt(), RegFieldDesc(s"debug_flags_${i}", "", volatile=true))}),
flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt(), RegFieldDesc(s"debug_flags_$i", "", volatile=true))}),
ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"),
DebugRomContents().zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W),
RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
DebugRomContents().zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
)
// Override System Bus accesses with dmactive reset.