Merge branch 'master' into pipeline-mmio
This commit is contained in:
Henry Cook
GitHub
@ -121,7 +121,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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tlb.io.req.bits.sfence.valid := s1_sfence
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tlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
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tlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)
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tlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data
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tlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data.data
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tlb.io.req.bits.passthrough := s1_req.phys
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tlb.io.req.bits.vaddr := s1_req.addr
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tlb.io.req.bits.instruction := false
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@ -155,6 +155,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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val s1_data_way = Mux(inWriteback, releaseWay, s1_hit_way)
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val s1_data = Mux1H(s1_data_way, data.io.resp) // retime into s2 if critical
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val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes).mask)
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val s2_valid = Reg(next=s1_valid_masked && !s1_sfence, init=Bool(false)) && !io.cpu.s2_xcpt.asUInt.orR
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val s2_probe = Reg(next=s1_probe, init=Bool(false))
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@ -229,10 +230,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write)
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val pstore1_typ = RegEnable(s1_req.typ, s1_valid_not_nacked && s1_write)
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val pstore1_addr = RegEnable(s1_paddr, s1_valid_not_nacked && s1_write)
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val pstore1_data = RegEnable(io.cpu.s1_data, s1_valid_not_nacked && s1_write)
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val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write)
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val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write)
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val pstore1_storegen = new StoreGen(pstore1_typ, pstore1_addr, pstore1_data, wordBytes)
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val pstore1_storegen_data = Wire(init = pstore1_storegen.data)
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val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write)
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val pstore1_storegen_data = Wire(init = pstore1_data)
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val pstore1_amo = Bool(usingAtomics) && isRead(pstore1_cmd)
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val pstore_drain_structural = pstore1_valid && pstore2_valid && ((s1_valid && s1_write) || pstore1_amo)
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val pstore_drain_opportunistic = !(io.cpu.req.valid && isRead(io.cpu.req.bits.cmd))
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@ -252,21 +253,20 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val pstore2_addr = RegEnable(pstore1_addr, advance_pstore1)
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val pstore2_way = RegEnable(pstore1_way, advance_pstore1)
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val pstore2_storegen_data = RegEnable(pstore1_storegen_data, advance_pstore1)
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val pstore2_storegen_mask = RegEnable(pstore1_storegen.mask, advance_pstore1)
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val pstore2_storegen_mask = RegEnable(pstore1_mask, advance_pstore1)
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dataArb.io.in(0).valid := pstore_drain
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dataArb.io.in(0).bits.write := true
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dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr)
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dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way)
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dataArb.io.in(0).bits.wdata := Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_storegen_data))
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val pstore_mask_shift = Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1,offsetlsb) << wordOffBits
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dataArb.io.in(0).bits.wmask := Mux(pstore2_valid, pstore2_storegen_mask, pstore1_storegen.mask) << pstore_mask_shift
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dataArb.io.in(0).bits.wmask := Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask) << pstore_mask_shift
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// store->load RAW hazard detection
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val s1_storegen = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes)
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val s1_idx = s1_req.addr(idxMSB, wordOffBits)
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val s1_raw_hazard = s1_read &&
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((pstore1_valid && pstore1_addr(idxMSB, wordOffBits) === s1_idx && (pstore1_storegen.mask & s1_storegen.mask).orR) ||
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(pstore2_valid && pstore2_addr(idxMSB, wordOffBits) === s1_idx && (pstore2_storegen_mask & s1_storegen.mask).orR))
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((pstore1_valid && pstore1_addr(idxMSB, wordOffBits) === s1_idx && (pstore1_mask & s1_mask).orR) ||
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(pstore2_valid && pstore2_addr(idxMSB, wordOffBits) === s1_idx && (pstore2_storegen_mask & s1_mask).orR))
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when (s1_valid && s1_raw_hazard) { s1_nack := true }
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metaWriteArb.io.in(0).valid := (s2_valid_hit && s2_update_meta) || (s2_victimize && !s2_victim_dirty)
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@ -279,8 +279,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR
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val acquire_address = s2_req_block_addr
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val access_address = s2_req.addr
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val a_size = s2_req.typ(MT_SZ-2, 0)
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val a_data = Fill(beatWords, pstore1_storegen.data)
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val a_size = mtSize(s2_req.typ)
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val a_data = Fill(beatWords, pstore1_data)
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val acquire = if (edge.manager.anySupportAcquireB) {
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edge.Acquire(UInt(0), acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
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} else {
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@ -517,14 +517,14 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes)
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io.cpu.resp.bits.data := loadgen.data | s2_sc_fail
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io.cpu.resp.bits.data_word_bypass := loadgen.wordData
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io.cpu.resp.bits.data_raw := s2_data_word
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io.cpu.resp.bits.store_data := pstore1_data
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// AMOs
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if (usingAtomics) {
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val amoalu = Module(new AMOALU(xLen))
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amoalu.io.addr := pstore1_addr
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amoalu.io.mask := pstore1_mask
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amoalu.io.cmd := pstore1_cmd
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amoalu.io.typ := pstore1_typ
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amoalu.io.lhs := s2_data_word
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amoalu.io.rhs := pstore1_data
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pstore1_storegen_data := amoalu.io.out
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@ -103,6 +103,7 @@ class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
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val replay = Bool()
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val has_data = Bool()
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val data_word_bypass = Bits(width = coreDataBits)
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val data_raw = Bits(width = coreDataBits)
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val store_data = Bits(width = coreDataBits)
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}
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@ -117,11 +118,16 @@ class HellaCacheExceptions extends Bundle {
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val ae = new AlignmentExceptions
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}
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class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) {
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val data = UInt(width = coreDataBits)
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val mask = UInt(width = coreDataBytes)
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}
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// interface between D$ and processor/DTLB
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class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Decoupled(new HellaCacheReq)
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val s1_kill = Bool(OUTPUT) // kill previous cycle's req
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val s1_data = Bits(OUTPUT, coreDataBits) // data for previous cycle's req
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val s1_data = new HellaCacheWriteData().asOutput // data for previous cycle's req
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val s2_nack = Bool(INPUT) // req from two cycles ago is rejected
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// performance events
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@ -129,7 +129,7 @@ class IDecode(implicit val p: Parameters) extends DecodeConstants
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class SDecode(implicit val p: Parameters) extends DecodeConstants
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{
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val table: Array[(BitPat, List[BitPat])] = Array(
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SFENCE_VMA->List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_SFENCE, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N),
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SFENCE_VMA->List(Y,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_SFENCE, MT_W, N,N,N,N,N,N,CSR.N,N,N,N,N),
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SRET-> List(Y,N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N,N))
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}
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@ -69,20 +69,18 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
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}
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val req = Reg(new HellaCacheReq)
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val req_cmd_sc = req.cmd === M_XSC
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val grant_word = Reg(UInt(width = wordBits))
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val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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io.req.ready := (state === s_idle)
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val storegen = new StoreGen(req.typ, req.addr, req.data, wordBytes)
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val loadgen = new LoadGen(req.typ, mtSigned(req.typ), req.addr, grant_word, req_cmd_sc, wordBytes)
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val loadgen = new LoadGen(req.typ, mtSigned(req.typ), req.addr, grant_word, false.B, wordBytes)
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val a_source = UInt(id)
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val a_address = req.addr
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val a_size = storegen.size
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val a_data = Fill(beatWords, storegen.data)
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val a_size = mtSize(req.typ)
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val a_data = Fill(beatWords, req.data)
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val get = edge.Get(a_source, a_address, a_size)._2
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val put = edge.Put(a_source, a_address, a_size, a_data)._2
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@ -99,9 +97,10 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
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M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))
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} else {
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// If no managers support atomics, assert fail if processor asks for them
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assert (!isAMO(req.cmd))
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assert(state === s_idle || !isAMO(req.cmd))
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Wire(new TLBundleA(edge.bundle))
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}
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assert(state === s_idle || req.cmd =/= M_XSC)
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io.mem_access.valid := (state === s_mem_access)
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io.mem_access.bits := Mux(isAMO(req.cmd), atomics, Mux(isRead(req.cmd), get, put))
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@ -110,7 +109,7 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
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io.resp.valid := (state === s_resp)
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io.resp.bits := req
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io.resp.bits.has_data := isRead(req.cmd)
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io.resp.bits.data := loadgen.data | req_cmd_sc
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io.resp.bits.data := loadgen.data
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io.resp.bits.store_data := req.data
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io.resp.bits.replay := Bool(true)
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@ -696,6 +695,8 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
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val s1_read = isRead(s1_req.cmd)
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val s1_write = isWrite(s1_req.cmd)
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val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
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// check for unsupported operations
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assert(!s1_valid || !s1_req.cmd.isOneOf(M_PWR))
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val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
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io.ptw <> dtlb.io.ptw
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@ -703,7 +704,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
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dtlb.io.req.bits.sfence.valid := s1_sfence
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dtlb.io.req.bits.sfence.bits.rs1 := s1_req.typ(0)
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dtlb.io.req.bits.sfence.bits.rs2 := s1_req.typ(1)
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dtlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data
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dtlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data.data
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dtlb.io.req.bits.passthrough := s1_req.phys
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dtlb.io.req.bits.vaddr := s1_req.addr
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dtlb.io.req.bits.instruction := Bool(false)
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@ -736,7 +737,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
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s2_req.phys := s1_req.phys
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s2_req.addr := s1_addr
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when (s1_write) {
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s2_req.data := Mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.s1_data)
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s2_req.data := Mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.s1_data.data)
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}
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when (s1_recycled) { s2_req.data := s1_req.data }
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s2_req.tag := s1_req.tag
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@ -927,10 +928,9 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
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val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits)))
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val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
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val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes)
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amoalu.io.addr := s2_req.addr
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amoalu.io.mask := new StoreGen(s2_req.typ, s2_req.addr, 0.U, xLen/8).mask
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amoalu.io.cmd := s2_req.cmd
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amoalu.io.typ := s2_req.typ
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amoalu.io.lhs := s2_data_word
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amoalu.io.rhs := s2_req.data
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@ -972,6 +972,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
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io.cpu.s2_nack := s2_valid && s2_nack
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io.cpu.resp := Mux(mshrs.io.resp.ready, uncache_resp, cache_resp)
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io.cpu.resp.bits.data_word_bypass := loadgen.wordData
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io.cpu.resp.bits.data_raw := s2_data_word
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io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
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io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next
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@ -394,7 +394,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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mem_reg_pc := ex_reg_pc
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mem_reg_wdata := alu.io.out
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when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc)) {
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mem_reg_rs2 := ex_rs(1)
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val typ = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_ctrl.mem_type)
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mem_reg_rs2 := new uncore.util.StoreGen(typ, 0.U, ex_rs(1), coreDataBytes).data
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}
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}
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@ -625,7 +626,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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io.dmem.req.bits.phys := Bool(false)
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io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
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io.dmem.invalidate_lr := wb_xcpt
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io.dmem.s1_data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
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io.dmem.s1_data.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
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io.dmem.s1_kill := killm_common || mem_breakpoint
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io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
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@ -22,9 +22,9 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
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resources = device.reg,
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsArithmetic = if (usingAtomics) TransferSizes(1, coreDataBytes) else TransferSizes.none,
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supportsLogical = if (usingAtomics) TransferSizes(1, coreDataBytes) else TransferSizes.none,
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supportsPutPartial = TransferSizes.none, // Can't support PutPartial
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supportsArithmetic = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,
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supportsLogical = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,
|
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supportsPutPartial = TransferSizes(1, coreDataBytes),
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supportsPutFull = TransferSizes(1, coreDataBytes),
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supportsGet = TransferSizes(1, coreDataBytes),
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fifoId = Some(0))), // requests handled in FIFO order
|
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@ -48,13 +48,14 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
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when (io.dmem.req.fire()) { state := s_wait }
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val acq = Reg(tl_in.a.bits)
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when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data }
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when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data_raw }
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when (tl_in.a.fire()) { acq := tl_in.a.bits }
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def formCacheReq(a: TLBundleA) = {
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val req = Wire(new HellaCacheReq)
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req.cmd := MuxLookup(a.opcode, Wire(M_XRD), Array(
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TLMessages.PutFullData -> M_XWR,
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TLMessages.PutPartialData -> M_PWR,
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TLMessages.ArithmeticData -> MuxLookup(a.param, Wire(M_XRD), Array(
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TLAtomics.MIN -> M_XA_MIN,
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TLAtomics.MAX -> M_XA_MAX,
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@ -67,9 +68,8 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
|
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TLAtomics.AND -> M_XA_AND,
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TLAtomics.SWAP -> M_XA_SWAP)),
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TLMessages.Get -> M_XRD))
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// treat all loads as full words, so bytes appear in correct lane
|
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req.typ := Mux(edge.hasData(a), a.size, log2Ceil(coreDataBytes))
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req.addr := Mux(edge.hasData(a), a.address, ~(~a.address | (coreDataBytes-1)))
|
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req.typ := a.size
|
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req.addr := a.address
|
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req.tag := UInt(0)
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req.phys := true
|
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req
|
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@ -79,23 +79,16 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
|
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io.dmem.req.valid := (tl_in.a.valid && ready) || state === s_replay
|
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tl_in.a.ready := io.dmem.req.ready && ready
|
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io.dmem.req.bits := formCacheReq(Mux(state === s_replay, acq, tl_in.a.bits))
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// the TL data is already in the correct byte lane, but the D$
|
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// expects right-justified store data, so that it can steer the bytes.
|
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io.dmem.s1_data := new LoadGen(acq.size, Bool(false), acq.address(log2Ceil(coreDataBytes)-1,0), acq.data, Bool(false), coreDataBytes).data
|
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io.dmem.s1_data.data := acq.data
|
||||
io.dmem.s1_data.mask := acq.mask
|
||||
io.dmem.s1_kill := false
|
||||
io.dmem.invalidate_lr := false
|
||||
|
||||
// place AMO data in correct word lane
|
||||
val minAMOBytes = 4
|
||||
val grantData = Mux(io.dmem.resp.valid, io.dmem.resp.bits.data, acq.data)
|
||||
val alignedGrantData =
|
||||
Mux(edge.hasData(acq) && (acq.size <= log2Ceil(minAMOBytes)), Fill(coreDataBytes/minAMOBytes, grantData(8*minAMOBytes-1, 0)), grantData)
|
||||
|
||||
tl_in.d.valid := io.dmem.resp.valid || state === s_grant
|
||||
tl_in.d.bits := Mux(acq.opcode === TLMessages.PutFullData,
|
||||
tl_in.d.bits := Mux(acq.opcode.isOneOf(TLMessages.PutFullData, TLMessages.PutPartialData),
|
||||
edge.AccessAck(acq, UInt(0)),
|
||||
edge.AccessAck(acq, UInt(0), UInt(0)))
|
||||
tl_in.d.bits.data := alignedGrantData
|
||||
tl_in.d.bits.data := Mux(io.dmem.resp.valid, io.dmem.resp.bits.data_raw, acq.data)
|
||||
|
||||
// Tie off unused channels
|
||||
tl_in.b.valid := Bool(false)
|
||||
|
||||
@ -123,7 +123,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
|
||||
io.cache.invalidate_lr := io.requestor.invalidate_lr
|
||||
io.cache.req <> req_arb.io.out
|
||||
io.cache.s1_kill := io.cache.s2_nack
|
||||
io.cache.s1_data := RegEnable(req_arb.io.out.bits.data, s0_req_fire)
|
||||
io.cache.s1_data.data := RegEnable(req_arb.io.out.bits.data, s0_req_fire)
|
||||
|
||||
replayq.io.nack.valid := (io.cache.s2_nack || s2_kill) && s2_req_fire
|
||||
replayq.io.nack.bits := s2_req_tag
|
||||
|
||||
Reference in New Issue
Block a user