riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

NASTIErrorSlave should print address

Browse Source
This commit is contained in:
Howard Mao 2015-09-18 09:42:41 -07:00
parent 4c3c3c630e
commit 4db6124b2a
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
junctions/src/main/scala/nasti.scala
View File

@ -348,6 +348,9 @@ class NASTIReadDataArbiter(arbN: Int) extends NASTIModule {
class NASTIErrorSlave extends NASTIModule { class NASTIErrorSlave extends NASTIModule {
val io = new NASTISlaveIO val io = new NASTISlaveIO
when (io.ar.fire()) { printf("Invalid read address %x\n", io.ar.bits.addr) }
when (io.aw.fire()) { printf("Invalid write address %x\n", io.aw.bits.addr) }
val r_queue = Module(new Queue(UInt(width = nastiRIdBits), 2)) val r_queue = Module(new Queue(UInt(width = nastiRIdBits), 2))
r_queue.io.enq.valid := io.ar.valid r_queue.io.enq.valid := io.ar.valid
r_queue.io.enq.bits := io.ar.bits.id r_queue.io.enq.bits := io.ar.bits.id