diff --git a/project/build.properties b/project/build.properties
new file mode 100644
index 00000000..c2df4283
--- /dev/null
+++ b/project/build.properties
@@ -0,0 +1 @@
+sbt.version=0.13.0-RC2
diff --git a/project/build.scala b/project/build.scala
index 7e870dcc..96c68556 100644
--- a/project/build.scala
+++ b/project/build.scala
@@ -6,14 +6,16 @@ import Keys._
 object BuildSettings extends Build {
   val buildOrganization = "berkeley"
   val buildVersion = "1.1"
-  val buildScalaVersion = "2.9.2"
+  val buildScalaVersion = "2.10.2"
 
   val buildSettings = Defaults.defaultSettings ++ Seq (
     //unmanagedBase <<= baseDirectory { base => base / ".." / custom_lib" },
     organization := buildOrganization,
     version      := buildVersion,
     scalaVersion := buildScalaVersion,
-    traceLevel   := 15
+    traceLevel   := 15,
+    scalacOptions ++= Seq("-deprecation","-unchecked"),
+    libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value
   )
 
   lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings)
diff --git a/riscv-rocket b/riscv-rocket
index 9ace637d..525a41f6 160000
--- a/riscv-rocket
+++ b/riscv-rocket
@@ -1 +1 @@
-Subproject commit 9ace637d7b28e2aff7289fea094f5d8d8eb83212
+Subproject commit 525a41f6f93bf9906c99c04dacaf75fa97723e57
diff --git a/sbt-launch.jar b/sbt-launch.jar
index 070ecb01..c91a2431 100644
Binary files a/sbt-launch.jar and b/sbt-launch.jar differ
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 5a913957..5f7d465f 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -1,8 +1,6 @@
 package referencechip
 
 import Chisel._
-import Node._
-import uncore.Constants._
 import uncore._
 import rocket._
 import rocket.Util._
@@ -10,203 +8,13 @@ import ReferenceChipBackend._
 import scala.collection.mutable.ArrayBuffer
 import scala.collection.mutable.HashMap
 
-object TileLinkHeaderAppender {
-  def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: UncoreConfiguration) = {
-    val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.meta.bits.payload.clone, in.data.bits.payload.clone)
-    shim.io.in <> in
-    shim.io.out
-  }
-  def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: UncoreConfiguration) = {
-    val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.bits.payload.clone, new AcquireData)
-    shim.io.in.meta <> in
-    shim.io.out.meta
-  }
-}
-
-class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(metadata: => T, data: => U)(implicit conf: UncoreConfiguration) extends Component {
-  implicit val ln = conf.ln
-  val io = new Bundle {
-    val in = new ClientSourcedDataIO()((new LogicalNetworkIO){ metadata }, (new LogicalNetworkIO){ data }).flip
-    val out = new ClientSourcedDataIO()((new LogicalNetworkIO){ metadata }, (new LogicalNetworkIO){ data })
-  }
-
-  val meta_q = Queue(io.in.meta)
-  val data_q = Queue(io.in.data)
-  if(nBanks == 1) {
-    io.out.meta.bits.payload := meta_q.bits.payload
-    io.out.meta.bits.header.src := UFix(clientId)
-    io.out.meta.bits.header.dst := UFix(0)
-    io.out.meta.valid := meta_q.valid
-    meta_q.ready := io.out.meta.ready
-    io.out.data.bits.payload := data_q.bits.payload
-    io.out.data.bits.header.src := UFix(clientId)
-    io.out.data.bits.header.dst := UFix(0)
-    io.out.data.valid := data_q.valid
-    data_q.ready := io.out.data.ready
-  } else {
-    val meta_has_data = conf.co.messageHasData(meta_q.bits.payload)
-    val addr_q = (new Queue(2, pipe = true, flow = true)){io.in.meta.bits.payload.addr.clone}
-    val data_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
-    val data_cnt_up = data_cnt + UFix(1)
-
-    io.out.meta.bits.payload := meta_q.bits.payload
-    io.out.meta.bits.header.src := UFix(clientId)
-    io.out.meta.bits.header.dst := addrConvert(meta_q.bits.payload.addr)
-    io.out.data.bits.payload := meta_q.bits.payload
-    io.out.data.bits.header.src := UFix(clientId)
-    io.out.data.bits.header.dst := addrConvert(addr_q.io.deq.bits)
-    addr_q.io.enq.bits := meta_q.bits.payload.addr
-
-    io.out.meta.valid := meta_q.valid && addr_q.io.enq.ready
-    meta_q.ready := io.out.meta.ready && addr_q.io.enq.ready
-    io.out.data.valid := data_q.valid && addr_q.io.deq.valid
-    data_q.ready := io.out.data.ready && addr_q.io.deq.valid
-    addr_q.io.enq.valid := meta_q.valid && io.out.meta.ready && meta_has_data
-    addr_q.io.deq.ready := Bool(false)
-
-    when(data_q.valid && data_q.ready) {
-      data_cnt := data_cnt_up
-      when(data_cnt_up === UFix(0)) {
-        addr_q.io.deq.ready := Bool(true)
-      }
-    }
-  }
-}
-
-class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfiguration) extends Component {
-  implicit val ln = conf.ln
-  val io = new Bundle {
-    val uncached = new UncachedTileLinkIO().flip
-    val mem = new ioMem
-  }
-  val mem_cmd_q = (new Queue(qDepth)){new MemReqCmd}
-  val mem_data_q = (new Queue(qDepth)){new MemData}
-  mem_cmd_q.io.enq.valid := io.uncached.acquire.meta.valid
-  io.uncached.acquire.meta.ready := mem_cmd_q.io.enq.ready 
-  mem_cmd_q.io.enq.bits.rw := conf.co.needsOuterWrite(io.uncached.acquire.meta.bits.payload.a_type, UFix(0))
-  mem_cmd_q.io.enq.bits.tag := io.uncached.acquire.meta.bits.payload.client_xact_id
-  mem_cmd_q.io.enq.bits.addr := io.uncached.acquire.meta.bits.payload.addr
-  mem_data_q.io.enq.valid := io.uncached.acquire.data.valid
-  io.uncached.acquire.data.ready := mem_data_q.io.enq.ready
-  mem_data_q.io.enq.bits.data := io.uncached.acquire.data.bits.payload.data 
-  io.uncached.grant.valid := io.mem.resp.valid
-  io.mem.resp.ready := io.uncached.grant.ready
-  io.uncached.grant.bits.payload.data := io.mem.resp.bits.data
-  io.uncached.grant.bits.payload.client_xact_id := io.mem.resp.bits.tag
-  io.uncached.grant.bits.payload.master_xact_id := UFix(0) // DNC
-  io.uncached.grant.bits.payload.g_type := UFix(0) // DNC
-  io.mem.req_cmd <> mem_cmd_q.io.deq
-  io.mem.req_data <> mem_data_q.io.deq
-}
-
-class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.ln) {
-  implicit val lnConf = conf.ln
-  type TileLinkType = TileLinkIO
-  val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkType).flip}; case h:MasterCoherenceAgent => {new TileLinkType}})){ new TileLinkType }
-  implicit val pconf = new PhysicalNetworkConfiguration(conf.ln.nEndpoints, conf.ln.idBits) // Same config for all networks
-
-  type FBCIO[T <: Data] = FIFOIO[BasicCrossbarIO[T]]
-  type FLNIO[T <: Data] = FIFOIO[LogicalNetworkIO[T]]
-  type PBCIO[M <: Data, D <: Data] = PairedDataIO[BasicCrossbarIO[M], BasicCrossbarIO[D]]
-  type PLNIO[M <: Data, D <: Data] = PairedDataIO[LogicalNetworkIO[M], LogicalNetworkIO[D]]
-  type FromCrossbar[T <: Data] = FBCIO[T] => FLNIO[T]
-  type ToCrossbar[T <: Data] = FLNIO[T] => FBCIO[T]
-
-  def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
-    val out = new FIFOIO()(new LogicalNetworkIO()(in.bits.payload.clone)).asDirectionless
-    out.bits.header := in.bits.header
-    out.bits.payload := in.bits.payload
-    out.valid := in.valid
-    in.ready := out.ready
-    out
-  }
-  def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
-    val out = DefaultFromCrossbarShim(in)
-    out.bits.header.src := in.bits.header.src - UFix(conf.ln.nMasters)
-    out
-  }
-  def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
-    val out = DefaultFromCrossbarShim(in)
-    out.bits.header.dst := in.bits.header.dst - UFix(conf.ln.nMasters)
-    out
-  }
-  def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
-    val out = new FIFOIO()(new BasicCrossbarIO()(in.bits.payload.clone)).asDirectionless
-    out.bits.header := in.bits.header
-    out.bits.payload := in.bits.payload
-    out.valid := in.valid
-    in.ready := out.ready
-    out
-  }
-  def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
-    val out = DefaultToCrossbarShim(in)
-    out.bits.header.dst := in.bits.header.dst + UFix(conf.ln.nMasters)
-    out
-  }
-  def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
-    val out = DefaultToCrossbarShim(in)
-    out.bits.header.src := in.bits.header.src + UFix(conf.ln.nMasters)
-    out
-  }
-
-  def doFIFOInputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: ToCrossbar[T]) = {
-    val s = shim(log_io)
-    phys_in.valid := s.valid
-    phys_in.bits := s.bits
-    s.ready := phys_in.ready
-    phys_out.ready := Bool(false)
-  }
-  def doFIFOOutputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: FromCrossbar[T]) = {
-    val s = shim(phys_out)
-    log_io.valid := s.valid
-    log_io.bits := s.bits
-    s.ready := log_io.ready
-    phys_in.valid := Bool(false)
-  }
-  //TODO: Change all the manifest stuff to use TypeTags in Scala 2.11
-  def doFIFOHookup[S <: CoherenceAgentRole: ClassManifest, T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
-    if(scala.reflect.ClassManifest.fromClass(end.getClass) <:< classManifest[S]) // end.getClass is a subtype of S
-      doFIFOInputHookup(phys_in, phys_out, log_io, inShim)
-    else doFIFOOutputHookup(phys_in, phys_out, log_io, outShim)
-  }
-  def doClientSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
-    doFIFOHookup[ClientCoherenceAgent, T](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim)
-  def doMasterSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
-    doFIFOHookup[MasterCoherenceAgent, T](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim)
-    
-  def doPairedDataHookup[S <: CoherenceAgentRole : ClassManifest, T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
-    if(scala.reflect.ClassManifest.fromClass(end.getClass) <:< classManifest[S]) {
-      doFIFOInputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, inShim)
-      doFIFOInputHookup[R](phys_in.data, phys_out.data, log_io.data, inShimD)
-    } else {
-      doFIFOOutputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, outShim)
-      doFIFOOutputHookup[R](phys_in.data, phys_out.data, log_io.data, outShimD)
-    }
-  }
-  def doClientSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
-    doPairedDataHookup[ClientCoherenceAgent, T, R](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim)
-  def doMasterSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
-    doPairedDataHookup[MasterCoherenceAgent, T, R](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim)
-
-
-  def acqHasData(acq: BasicCrossbarIO[Acquire]) = conf.co.messageHasData(acq.payload)
-  val acq_net = new PairedCrossbar(REFILL_CYCLES, acqHasData _)(new Acquire, new AcquireData)
-  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) }
-
-  def relHasData(rel: BasicCrossbarIO[Release]) = conf.co.messageHasData(rel.payload)
-  val rel_net = new PairedCrossbar(REFILL_CYCLES, relHasData _)(new Release, new ReleaseData)
-  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }
-
-  val probe_net = new BasicCrossbar()(new Probe)
-  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) }
-
-  val grant_net = new BasicCrossbar()(new Grant)
-  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) }
-
-  val ack_net = new BasicCrossbar()(new GrantAck)
-  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) }
-
-  val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net)
+object DummyTopLevelConstants extends uncore.constants.CoherenceConfigConstants {
+  val NTILES = 2
+  val NBANKS = 1
+  val HTIF_WIDTH = 16
+  val ENABLE_SHARING = true
+  val ENABLE_CLEAN_EXCLUSIVE = true
+  val HAS_VEC = true
 }
 
 object ReferenceChipBackend {
@@ -277,14 +85,13 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
     val mem = new ioMem
   }
 
-  import rocket.Constants._
-
   val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1, 
                                     idBits = log2Up(conf.ln.nEndpoints+1)+1,
                                     nClients = conf.ln.nClients+1)
   val ucWithHtifConf = conf.copy(ln = lnWithHtifConf)
   require(clientEndpoints.length == lnWithHtifConf.nClients)
   val masterEndpoints = (0 until lnWithHtifConf.nMasters).map(new L2CoherenceAgent(_)(ucWithHtifConf))
+  val incoherentWithHtif = io.incoherent :+ Bool(true)
 
   val llc_tag_leaf = Mem(512, seqRead = true) { Bits(width = 152) }
   val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
@@ -294,7 +101,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
 
   val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(ucWithHtifConf)
   net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
-  masterEndpoints.map{ _.io.incoherent zip (io.incoherent ++ List(Bool(true))) map { case (m, c) => m := c } }
+  masterEndpoints.map{ _.io.incoherent zip incoherentWithHtif map { case (m, c) => m := c } }
 
   val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
   if(lnWithHtifConf.nMasters > 1) {
@@ -415,13 +222,6 @@ class TopIO(htif_width: Int) extends Bundle  {
   val mem     = new ioMem
 }
 
-object DummyTopLevelConstants extends _root_.uncore.constants.CoherenceConfigConstants {
-  val NTILES = 2
-  val NBANKS = 1
-  val HTIF_WIDTH = 16
-  val ENABLE_SHARING = true
-  val ENABLE_CLEAN_EXCLUSIVE = true
-}
 import DummyTopLevelConstants._
 
 class MemDessert extends Component {
@@ -450,7 +250,7 @@ class Top extends Component {
   val dc = DCacheConfig(128, 4, co, ntlb = 8,
                         nmshr = 2, nrpq = 16, nsdq = 17)
   val rc = RocketConfiguration(lnConf, co, ic, dc,
-                               fpu = true, vec = true)
+                               fpu = true, vec = HAS_VEC)
   val tileList = (0 until NTILES).map(r => new Tile(resetSignal = resetSigs(r))(rc))
   val uncore = new Uncore(HTIF_WIDTH, tileList)
 
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index e71483c5..da672d28 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -4,7 +4,6 @@ import Chisel._
 import Node._
 import uncore._
 import rocket._
-import rocket.Constants._
 
 class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
 {
@@ -16,8 +15,6 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
     val mem = new ioMem
   }
 
-  import rocket.Constants._
-
   val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1, 
                                     idBits = log2Up(conf.ln.nEndpoints+1)+1,
                                     nClients = conf.ln.nClients+1)
diff --git a/src/main/scala/network.scala b/src/main/scala/network.scala
new file mode 100644
index 00000000..e7578854
--- /dev/null
+++ b/src/main/scala/network.scala
@@ -0,0 +1,224 @@
+package referencechip
+
+import Chisel._
+import uncore._
+import scala.reflect._
+
+object TileLinkHeaderAppender {
+  def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: UncoreConfiguration) = {
+    val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.meta.bits.payload.clone, in.data.bits.payload.clone)
+    shim.io.in <> in
+    shim.io.out
+  }
+  def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: UncoreConfiguration) = {
+    val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.bits.payload.clone, new AcquireData)
+    shim.io.in.meta <> in
+    shim.io.out.meta
+  }
+}
+
+class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(metadata: => T, data: => U)(implicit conf: UncoreConfiguration) extends Component {
+  implicit val ln = conf.ln
+  val io = new Bundle {
+    val in = new ClientSourcedDataIO()((new LogicalNetworkIO){ metadata }, (new LogicalNetworkIO){ data }).flip
+    val out = new ClientSourcedDataIO()((new LogicalNetworkIO){ metadata }, (new LogicalNetworkIO){ data })
+  }
+
+  val meta_q = Queue(io.in.meta)
+  val data_q = Queue(io.in.data)
+  if(nBanks == 1) {
+    io.out.meta.bits.payload := meta_q.bits.payload
+    io.out.meta.bits.header.src := UFix(clientId)
+    io.out.meta.bits.header.dst := UFix(0)
+    io.out.meta.valid := meta_q.valid
+    meta_q.ready := io.out.meta.ready
+    io.out.data.bits.payload := data_q.bits.payload
+    io.out.data.bits.header.src := UFix(clientId)
+    io.out.data.bits.header.dst := UFix(0)
+    io.out.data.valid := data_q.valid
+    data_q.ready := io.out.data.ready
+  } else {
+    val meta_has_data = conf.co.messageHasData(meta_q.bits.payload)
+    val addr_q = (new Queue(2, pipe = true, flow = true)){io.in.meta.bits.payload.addr.clone}
+    val data_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
+    val data_cnt_up = data_cnt + UFix(1)
+
+    io.out.meta.bits.payload := meta_q.bits.payload
+    io.out.meta.bits.header.src := UFix(clientId)
+    io.out.meta.bits.header.dst := addrConvert(meta_q.bits.payload.addr)
+    io.out.data.bits.payload := meta_q.bits.payload
+    io.out.data.bits.header.src := UFix(clientId)
+    io.out.data.bits.header.dst := addrConvert(addr_q.io.deq.bits)
+    addr_q.io.enq.bits := meta_q.bits.payload.addr
+
+    io.out.meta.valid := meta_q.valid && addr_q.io.enq.ready
+    meta_q.ready := io.out.meta.ready && addr_q.io.enq.ready
+    io.out.data.valid := data_q.valid && addr_q.io.deq.valid
+    data_q.ready := io.out.data.ready && addr_q.io.deq.valid
+    addr_q.io.enq.valid := meta_q.valid && io.out.meta.ready && meta_has_data
+    addr_q.io.deq.ready := Bool(false)
+
+    when(data_q.valid && data_q.ready) {
+      data_cnt := data_cnt_up
+      when(data_cnt_up === UFix(0)) {
+        addr_q.io.deq.ready := Bool(true)
+      }
+    }
+  }
+}
+
+//Adapter betweewn an UncachedTileLinkIO and a mem controller MemIO
+class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfiguration) extends Component {
+  implicit val ln = conf.ln
+  val io = new Bundle {
+    val uncached = new UncachedTileLinkIO().flip
+    val mem = new ioMem
+  }
+  val mem_cmd_q = (new Queue(qDepth)){new MemReqCmd}
+  val mem_data_q = (new Queue(qDepth)){new MemData}
+  mem_cmd_q.io.enq.valid := io.uncached.acquire.meta.valid
+  io.uncached.acquire.meta.ready := mem_cmd_q.io.enq.ready 
+  mem_cmd_q.io.enq.bits.rw := conf.co.needsOuterWrite(io.uncached.acquire.meta.bits.payload.a_type, UFix(0))
+  mem_cmd_q.io.enq.bits.tag := io.uncached.acquire.meta.bits.payload.client_xact_id
+  mem_cmd_q.io.enq.bits.addr := io.uncached.acquire.meta.bits.payload.addr
+  mem_data_q.io.enq.valid := io.uncached.acquire.data.valid
+  io.uncached.acquire.data.ready := mem_data_q.io.enq.ready
+  mem_data_q.io.enq.bits.data := io.uncached.acquire.data.bits.payload.data 
+  io.uncached.grant.valid := io.mem.resp.valid
+  io.mem.resp.ready := io.uncached.grant.ready
+  io.uncached.grant.bits.payload.data := io.mem.resp.bits.data
+  io.uncached.grant.bits.payload.client_xact_id := io.mem.resp.bits.tag
+  io.uncached.grant.bits.payload.master_xact_id := UFix(0) // DNC
+  io.uncached.grant.bits.payload.g_type := UFix(0) // DNC
+  io.mem.req_cmd <> mem_cmd_q.io.deq
+  io.mem.req_data <> mem_data_q.io.deq
+}
+
+class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.ln) {
+  implicit val lnConf = conf.ln
+  val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}})){ new TileLinkIO }
+  implicit val pconf = new PhysicalNetworkConfiguration(conf.ln.nEndpoints, conf.ln.idBits) // Same config for all networks
+
+  // Aliases for the various network IO bundle types
+  type FBCIO[T <: Data] = FIFOIO[PhysicalNetworkIO[T]]
+  type FLNIO[T <: Data] = FIFOIO[LogicalNetworkIO[T]]
+  type PBCIO[M <: Data, D <: Data] = PairedDataIO[PhysicalNetworkIO[M], PhysicalNetworkIO[D]]
+  type PLNIO[M <: Data, D <: Data] = PairedDataIO[LogicalNetworkIO[M], LogicalNetworkIO[D]]
+  type FromCrossbar[T <: Data] = FBCIO[T] => FLNIO[T]
+  type ToCrossbar[T <: Data] = FLNIO[T] => FBCIO[T]
+
+  // Shims for converting between logical network IOs and physical network IOs
+  //TODO: Could be less verbose if you could override subbundles after a <>
+  def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
+    val out = new FIFOIO()(new LogicalNetworkIO()(in.bits.payload.clone)).asDirectionless
+    out.bits.header := in.bits.header
+    out.bits.payload := in.bits.payload
+    out.valid := in.valid
+    in.ready := out.ready
+    out
+  }
+  def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
+    val out = DefaultFromCrossbarShim(in)
+    out.bits.header.src := in.bits.header.src - UFix(conf.ln.nMasters)
+    out
+  }
+  def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
+    val out = DefaultFromCrossbarShim(in)
+    out.bits.header.dst := in.bits.header.dst - UFix(conf.ln.nMasters)
+    out
+  }
+  def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
+    val out = new FIFOIO()(new PhysicalNetworkIO()(in.bits.payload.clone)).asDirectionless
+    out.bits.header := in.bits.header
+    out.bits.payload := in.bits.payload
+    out.valid := in.valid
+    in.ready := out.ready
+    out
+  }
+  def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
+    val out = DefaultToCrossbarShim(in)
+    out.bits.header.dst := in.bits.header.dst + UFix(conf.ln.nMasters)
+    out
+  }
+  def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
+    val out = DefaultToCrossbarShim(in)
+    out.bits.header.src := in.bits.header.src + UFix(conf.ln.nMasters)
+    out
+  }
+
+  // Make an individual connection between virtual and physical ports using
+  // a particular shim. Also seal the unused FIFO control signal.
+  def doFIFOInputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: ToCrossbar[T]) = {
+    val s = shim(log_io)
+    phys_in.valid := s.valid
+    phys_in.bits := s.bits
+    s.ready := phys_in.ready
+    phys_out.ready := Bool(false)
+  }
+
+  def doFIFOOutputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: FromCrossbar[T]) = {
+    val s = shim(phys_out)
+    log_io.valid := s.valid
+    log_io.bits := s.bits
+    s.ready := log_io.ready
+    phys_in.valid := Bool(false)
+  }
+
+  // Use reflection to determine whether a particular endpoint should be
+  // hooked up as an [input/output] for a FIFO nework that is transmiitting
+  // [client/master]-sourced messages.
+  def doFIFOHookup[S <: CoherenceAgentRole: ClassTag, T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
+    // Is end's type a subtype of S, the agent type associated with inputs?
+    if(classTag[S].runtimeClass.isInstance(end)) 
+      doFIFOInputHookup(phys_in, phys_out, log_io, inShim)
+    else 
+      doFIFOOutputHookup(phys_in, phys_out, log_io, outShim)
+  }
+
+  def doClientSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
+    doFIFOHookup[ClientCoherenceAgent, T](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim)
+
+  def doMasterSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) =
+    doFIFOHookup[MasterCoherenceAgent, T](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim)
+    
+  // Use reflection to determine whether a particular endpoint should be
+  // hooked up as an [input/output] for a Paired nework that is transmiitting
+  // [client/master]-sourced messages.
+  def doPairedDataHookup[S <: CoherenceAgentRole : ClassTag, T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = {
+    // Is end's type a subtype of S, the agent type associated with inputs?
+    if(classTag[S].runtimeClass.isInstance(end)) {
+      doFIFOInputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, inShim)
+      doFIFOInputHookup[R](phys_in.data, phys_out.data, log_io.data, inShimD)
+    } else {
+      doFIFOOutputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, outShim)
+      doFIFOOutputHookup[R](phys_in.data, phys_out.data, log_io.data, outShimD)
+    }
+  }
+
+  def doClientSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
+    doPairedDataHookup[ClientCoherenceAgent, T, R](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim)
+
+  def doMasterSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) =
+    doPairedDataHookup[MasterCoherenceAgent, T, R](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim)
+
+
+  // Actually instantiate the particular networks required for TileLink
+  def acqHasData(acq: PhysicalNetworkIO[Acquire]) = conf.co.messageHasData(acq.payload)
+  val acq_net = new PairedCrossbar(REFILL_CYCLES, acqHasData _)(new Acquire, new AcquireData)
+  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) }
+
+  def relHasData(rel: PhysicalNetworkIO[Release]) = conf.co.messageHasData(rel.payload)
+  val rel_net = new PairedCrossbar(REFILL_CYCLES, relHasData _)(new Release, new ReleaseData)
+  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }
+
+  val probe_net = new BasicCrossbar()(new Probe)
+  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) }
+
+  val grant_net = new BasicCrossbar()(new Grant)
+  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) }
+
+  val ack_net = new BasicCrossbar()(new GrantAck)
+  endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) }
+
+  val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net)
+}
diff --git a/uncore b/uncore
index cd75291f..a4566955 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit cd75291f2969e46fc6cf62c9519e675c27c06eb4
+Subproject commit a456695526f4d2b35d017841b4fe14d2ba97d8f4