riscv/rocket-chip
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Fix very far forward JALs

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We were sign-extending from the wrong bit, causing a backwards jump.
This commit is contained in:
Andrew Waterman 2014-01-13 00:55:48 -08:00
parent c546f66404
commit 4d236979bd
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/dpath.scala
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@ -174,7 +174,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
e(0))) e(0)))
} }
val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs(0), ex_reg_pc) val ex_br_base = Mux(io.ctrl.ex_jalr, ex_rs(0), ex_reg_pc)
val ex_br_offset = Mux(io.ctrl.ex_predicted_taken, SInt(4), ex_imm(19,0).toSInt) val ex_br_offset = Mux(io.ctrl.ex_predicted_taken, SInt(4), ex_imm(20,0).toSInt)
val ex_br64 = ex_br_base + ex_br_offset val ex_br64 = ex_br_base + ex_br_offset
val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs(0), ex_br64), vaSign(ex_reg_pc, ex_br64)) val ex_br_msb = Mux(io.ctrl.ex_jalr, vaSign(ex_rs(0), ex_br64), vaSign(ex_reg_pc, ex_br64))
val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0)) val ex_br_addr = Cat(ex_br_msb, ex_br64(VADDR_BITS-1,0))