From 4ccdbecb634b8bc5d49a8f241cb999187e1e1565 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 1 Nov 2017 11:03:45 -0700 Subject: [PATCH] Async covers (#1085) * cover: support covering cross-product of ready-valid * tilelink: AsyncCrossing now has covers for all flow control logic --- src/main/scala/tilelink/AsyncCrossing.scala | 11 +++++++++++ src/main/scala/util/Property.scala | 8 +++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/AsyncCrossing.scala b/src/main/scala/tilelink/AsyncCrossing.scala index 6dc65b0f..eb44cc15 100644 --- a/src/main/scala/tilelink/AsyncCrossing.scala +++ b/src/main/scala/tilelink/AsyncCrossing.scala @@ -6,6 +6,7 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ +import freechips.rocketchip.util.property._ import freechips.rocketchip.coreplex.{CrossingWrapper, AsynchronousCrossing} class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule @@ -20,11 +21,16 @@ class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyM out.a <> ToAsyncBundle(in.a, depth, sync) in.d <> FromAsyncBundle(out.d, sync) + cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") + cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, sync) out.c <> ToAsyncBundle(in.c, depth, sync) out.e <> ToAsyncBundle(in.e, depth, sync) + cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") + cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") + cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := Bool(false) in.c.ready := Bool(true) @@ -48,11 +54,16 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) out.a <> FromAsyncBundle(in.a, sync) in.d <> ToAsyncBundle(out.d, depth, sync) + cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") + cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, depth, sync) out.c <> FromAsyncBundle(in.c, sync) out.e <> FromAsyncBundle(in.e, sync) + cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") + cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") + cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := UInt(0) in.c.ridx := UInt(0) diff --git a/src/main/scala/util/Property.scala b/src/main/scala/util/Property.scala index f3c81672..7f020f9b 100644 --- a/src/main/scala/util/Property.scala +++ b/src/main/scala/util/Property.scala @@ -4,6 +4,7 @@ package freechips.rocketchip.util.property import Chisel._ import chisel3.internal.sourceinfo.{SourceInfo, SourceLine} +import chisel3.util.{ReadyValidIO} import freechips.rocketchip.config.{Field, Parameters} case object PropertyLibrary extends Field[BasePropertyLibrary](new DefaultPropertyLibrary) @@ -54,5 +55,10 @@ object cover { def apply(cond: Bool, label: String, message: String)(implicit sourceInfo: SourceInfo, p: Parameters): Unit = { p(PropertyLibrary).generateProperty(CoverPropertyParameters(cond, label, message)) } + def apply[T <: Data](rv: ReadyValidIO[T], label: String, message: String)(implicit sourceInfo: SourceInfo, p: Parameters): Unit = { + apply( rv.valid && rv.ready, label + "_FIRE", message + ": valid and ready") + apply( rv.valid && !rv.ready, label + "_STALL", message + ": valid and not ready") + apply(!rv.valid && rv.ready, label + "_IDLE", message + ": not valid and ready") + apply(!rv.valid && !rv.ready, label + "_FULL", message + ": not valid and not ready") + } } -