diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index d1f9f34d..311cfa3a 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -53,7 +53,7 @@ class BHT(implicit conf: BTBConfig) {
   val history = Reg(UInt(width = log2Up(conf.nbht)))
 }
 
-class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
+class BTBUpdate(implicit val conf: BTBConfig) extends BundleWithConf {
   val prediction = Valid(new BTBResp)
   val pc = UInt(width = conf.as.vaddrBits)
   val target = UInt(width = conf.as.vaddrBits)
@@ -63,17 +63,13 @@ class BTBUpdate(implicit conf: BTBConfig) extends Bundle {
   val isCall = Bool()
   val isReturn = Bool()
   val incorrectTarget = Bool()
-
-  override def clone = new BTBUpdate().asInstanceOf[this.type]
 }
 
-class BTBResp(implicit conf: BTBConfig) extends Bundle {
+class BTBResp(implicit val conf: BTBConfig) extends BundleWithConf {
   val taken = Bool()
   val target = UInt(width = conf.as.vaddrBits)
   val entry = UInt(width = conf.opaqueBits)
   val bht = new BHTResp
-
-  override def clone = new BTBResp().asInstanceOf[this.type]
 }
 
 // fully-associative branch target buffer
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index ee25d6ab..a2d02dba 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -168,7 +168,6 @@ class FPInput extends FPUCtrlSigs {
   val in1 = Bits(width = 65)
   val in2 = Bits(width = 65)
   val in3 = Bits(width = 65)
-  override def clone = new FPInput().asInstanceOf[this.type]
 }
 
 class FPToInt extends Module
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 9bc4c617..a9308086 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -29,18 +29,15 @@ case class ICacheConfig(sets: Int, assoc: Int,
   require(as.pgIdxBits >= untagbits)
 }
 
-class FrontendReq()(implicit conf: ICacheConfig) extends Bundle {
+class FrontendReq()(implicit val conf: ICacheConfig) extends BundleWithConf {
   val pc = UInt(width = conf.as.vaddrBits+1)
-  override def clone = new FrontendReq().asInstanceOf[this.type]
 }
 
-class FrontendResp(implicit conf: ICacheConfig) extends Bundle {
+class FrontendResp(implicit val conf: ICacheConfig) extends BundleWithConf {
   val pc = UInt(width = conf.as.vaddrBits+1)  // ID stage PC
   val data = Bits(width = conf.ibytes*8)
   val xcpt_ma = Bool()
   val xcpt_if = Bool()
-
-  override def clone = new FrontendResp().asInstanceOf[this.type]
 }
 
 class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle {
@@ -129,17 +126,15 @@ class Frontend(implicit c: ICacheConfig) extends Module
   io.cpu.btb_resp.bits := s2_btb_resp_bits
 }
 
-class ICacheReq(implicit c: ICacheConfig)  extends Bundle {
-  val idx = UInt(width = c.as.pgIdxBits)
-  val ppn = UInt(width = c.as.ppnBits) // delayed one cycle
+class ICacheReq(implicit val conf: ICacheConfig) extends BundleWithConf {
+  val idx = UInt(width = conf.as.pgIdxBits)
+  val ppn = UInt(width = conf.as.ppnBits) // delayed one cycle
   val kill = Bool() // delayed one cycle
-  override def clone = new ICacheReq().asInstanceOf[this.type]
 }
 
-class ICacheResp(implicit c: ICacheConfig) extends Bundle {
-  val data = Bits(width = c.ibytes*8)
-  val datablock = Bits(width = c.rowbits)
-  override def clone = new ICacheResp().asInstanceOf[this.type]
+class ICacheResp(implicit val conf: ICacheConfig) extends BundleWithConf {
+  val data = Bits(width = conf.ibytes*8)
+  val datablock = Bits(width = conf.rowbits)
 }
 
 class ICache(implicit c: ICacheConfig) extends Module
diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala
index 54320436..4f43bd41 100644
--- a/rocket/src/main/scala/multiplier.scala
+++ b/rocket/src/main/scala/multiplier.scala
@@ -4,21 +4,17 @@ import Chisel._
 import ALU._
 import Util._
 
-class MultiplierReq(implicit conf: RocketConfiguration) extends Bundle {
+class MultiplierReq(implicit val conf: RocketConfiguration) extends BundleWithConf {
   val fn = Bits(width = SZ_ALU_FN)
   val dw = Bits(width = SZ_DW)
   val in1 = Bits(width = conf.xprlen)
   val in2 = Bits(width = conf.xprlen)
   val tag = UInt(width = conf.nxprbits)
-
-  override def clone = new MultiplierReq().asInstanceOf[this.type]
 }
 
-class MultiplierResp(implicit conf: RocketConfiguration) extends Bundle {
+class MultiplierResp(implicit val conf: RocketConfiguration) extends BundleWithConf {
   val data = Bits(width = conf.xprlen)
   val tag = UInt(width = conf.nxprbits)
-
-  override def clone = new MultiplierResp().asInstanceOf[this.type]
 }
 
 class MultiplierIO(implicit conf: RocketConfiguration) extends Bundle {
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 20b2c256..42620e71 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -46,11 +46,6 @@ case class DCacheConfig(val sets: Int, val ways: Int,
   require(untagbits <= pgidxbits)
 }
 
-abstract trait DCacheBundle extends Bundle {
-  implicit val conf: DCacheConfig
-  override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
-}
-
 class StoreGen(typ: Bits, addr: Bits, dat: Bits)
 {
   val byte = typ === MT_B || typ === MT_BU
@@ -93,7 +88,7 @@ class Replay(implicit conf: DCacheConfig) extends HellaCacheReq {
   val sdq_id = UInt(width = log2Up(conf.nsdq))
 }
 
-class DataReadReq(implicit val conf: DCacheConfig) extends DCacheBundle {
+class DataReadReq(implicit val conf: DCacheConfig) extends BundleWithConf {
   val way_en = Bits(width = conf.ways)
   val addr   = Bits(width = conf.untagbits)
 }
@@ -122,7 +117,7 @@ class L1MetaReadReq(implicit conf: DCacheConfig) extends MetaReadReq {
 class InternalProbe(implicit conf: TileLinkConfiguration) extends Probe()(conf) 
   with HasClientTransactionId
 
-class WritebackReq(implicit val conf: DCacheConfig) extends DCacheBundle {
+class WritebackReq(implicit val conf: DCacheConfig) extends BundleWithConf {
   val tag = Bits(width = conf.tagbits)
   val idx = Bits(width = conf.idxbits)
   val way_en = Bits(width = conf.ways)
@@ -637,7 +632,7 @@ class AMOALU(implicit conf: DCacheConfig) extends Module {
   io.out := wmask & out | ~wmask & io.lhs
 }
 
-class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle {
+class HellaCacheReq(implicit val conf: DCacheConfig) extends BundleWithConf {
   val kill = Bool()
   val typ  = Bits(width = MT_SZ)
   val phys = Bool()
@@ -647,7 +642,7 @@ class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle {
   val cmd  = Bits(width = M_SZ)
 }
 
-class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle {
+class HellaCacheResp(implicit val conf: DCacheConfig) extends BundleWithConf {
   val nack = Bool() // comes 2 cycles after req.fire
   val replay = Bool()
   val typ = Bits(width = 3)
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index f72e0b14..1b42af49 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -4,15 +4,13 @@ import Chisel._
 import uncore._
 import Util._
 
-class PTWResp()(implicit conf: AddressSpaceConfiguration) extends Bundle {
+class PTWResp()(implicit val conf: AddressSpaceConfiguration) extends BundleWithConf {
   val error = Bool()
   val ppn = UInt(width = conf.ppnBits)
   val perm = Bits(width = conf.permBits)
-
-  override def clone = new PTWResp().asInstanceOf[this.type]
 }
 
-class TLBPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
+class TLBPTWIO()(implicit val conf: AddressSpaceConfiguration) extends BundleWithConf {
   val req = Decoupled(UInt(width = conf.vpnBits))
   val resp = Valid(new PTWResp).flip
   val status = new Status().asInput
@@ -20,7 +18,7 @@ class TLBPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
   val sret = Bool(INPUT)
 }
 
-class DatapathPTWIO()(implicit conf: AddressSpaceConfiguration) extends Bundle {
+class DatapathPTWIO()(implicit val conf: AddressSpaceConfiguration) extends BundleWithConf {
   val ptbr = UInt(INPUT, conf.paddrBits)
   val invalidate = Bool(INPUT)
   val sret = Bool(INPUT)
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index c3a9f5cf..3a3e2bf4 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -16,24 +16,20 @@ class RoCCInstruction extends Bundle
   val opcode = Bits(width = 7)
 }
 
-class RoCCCommand(implicit conf: RocketConfiguration) extends Bundle
+class RoCCCommand(implicit val conf: RocketConfiguration) extends BundleWithConf
 {
   val inst = new RoCCInstruction
   val rs1 = Bits(width = conf.xprlen)
   val rs2 = Bits(width = conf.xprlen)
-
-  override def clone = new RoCCCommand().asInstanceOf[this.type]
 }
 
-class RoCCResponse(implicit conf: RocketConfiguration) extends Bundle
+class RoCCResponse(implicit val conf: RocketConfiguration) extends BundleWithConf
 {
   val rd = Bits(width = 5)
   val data = Bits(width = conf.xprlen)
-
-  override def clone = new RoCCResponse().asInstanceOf[this.type]
 }
 
-class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
+class RoCCInterface(implicit val conf: RocketConfiguration) extends BundleWithConf
 {
   implicit val as = conf.as
   val cmd = Decoupled(new RoCCCommand).flip
@@ -49,8 +45,6 @@ class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
   val dptw = new TLBPTWIO
   val pptw = new TLBPTWIO
   val exception = Bool(INPUT)
-
-  override def clone = new RoCCInterface().asInstanceOf[this.type]
 }
 
 abstract class RoCC(conf: RocketConfiguration) extends Module
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 8014e0ca..067565f0 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -64,17 +64,15 @@ class PseudoLRU(n: Int)
   }
 }
 
-class TLBReq()(implicit conf: AddressSpaceConfiguration) extends Bundle
+class TLBReq()(implicit val conf: AddressSpaceConfiguration) extends BundleWithConf
 {
   val asid = UInt(width = conf.asidBits)
   val vpn = UInt(width = conf.vpnBits+1)
   val passthrough = Bool()
   val instruction = Bool()
-
-  override def clone = new TLBReq().asInstanceOf[this.type]
 }
 
-class TLBResp(entries: Int)(implicit conf: AddressSpaceConfiguration) extends Bundle
+class TLBResp(entries: Int)(implicit val conf: AddressSpaceConfiguration) extends BundleWithConf
 {
   // lookup responses
   val miss = Bool(OUTPUT)
@@ -83,8 +81,6 @@ class TLBResp(entries: Int)(implicit conf: AddressSpaceConfiguration) extends Bu
   val xcpt_ld = Bool(OUTPUT)
   val xcpt_st = Bool(OUTPUT)
   val xcpt_if = Bool(OUTPUT)
-
-  override def clone = new TLBResp(entries)(conf).asInstanceOf[this.type]
 }
 
 class TLB(entries: Int)(implicit conf: AddressSpaceConfiguration) extends Module
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index 4a0ef27d..82ead46c 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -21,6 +21,11 @@ object Util {
 
 import Util._
 
+abstract trait BundleWithConf extends Bundle {
+  val conf: AnyRef
+  override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
+}
+
 object Str
 {
   def apply(s: String): UInt = {