riscv/rocket-chip
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change the configuration interface of SlowIO

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This commit is contained in:
Howard Mao 2016-09-29 22:16:53 -07:00
parent 8730887baa
commit 4b86802b1a
1 changed files with 6 additions and 11 deletions
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17
src/main/scala/junctions/slowio.scala
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@ -11,20 +11,15 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
val in_fast = Decoupled(data) val in_fast = Decoupled(data)
val in_slow = Decoupled(data).flip val in_slow = Decoupled(data).flip
val clk_slow = Bool(OUTPUT) val clk_slow = Bool(OUTPUT)
val set_divisor = Valid(Bits(width = 32)).flip
val divisor = Bits(OUTPUT, 32) val divisor = UInt(INPUT, log2Up(divisor_max))
val hold = UInt(INPUT, log2Up(divisor_max))
} }
require(divisor_max >= 8 && divisor_max <= 65536 && isPow2(divisor_max)) require(divisor_max >= 8 && divisor_max <= 65536 && isPow2(divisor_max))
val divisor = Reg(init=UInt(divisor_max-1)) val divisor = Reg(init=UInt(divisor_max-1))
val d_shadow = Reg(init=UInt(divisor_max-1))
val hold = Reg(init=UInt(divisor_max/4-1)) val hold = Reg(init=UInt(divisor_max/4-1))
val h_shadow = Reg(init=UInt(divisor_max/4-1))
when (io.set_divisor.valid) {
d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0)
h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16)
}
io.divisor := (hold << 16) | divisor
val count = Reg{UInt(width = log2Up(divisor_max))} val count = Reg{UInt(width = log2Up(divisor_max))}
val myclock = Reg{Bool()} val myclock = Reg{Bool()}
@ -35,8 +30,8 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
val held = count === (divisor >> 1) + hold val held = count === (divisor >> 1) + hold
when (falling) { when (falling) {
divisor := d_shadow divisor := io.divisor
hold := h_shadow hold := io.hold
count := UInt(0) count := UInt(0)
myclock := Bool(false) myclock := Bool(false)
} }