riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Register Field: Add a more verbose description object

Browse Source 
Add versions of the RegField functions to take it in, and
update Example device to use it.
This commit is contained in:
Megan Wachs
2018-01-08 11:20:37 -08:00
parent 1bfdfacda0
commit 4ab1585a78
2 changed files with 79 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/main/scala/tilelink/Example.scala
View File

@ -20,7 +20,7 @@ trait ExampleModule extends HasRegMap
val io: ExampleBundle
val interrupts: Vec[Bool]
val state = RegInit(UInt(0))
val state = RegInit(UInt(0, width = params.num))
val pending = RegInit(UInt(0xf, width = 4))
io.gpio := state
@ -28,9 +28,15 @@ trait ExampleModule extends HasRegMap
regmap(
0 -> Seq(
RegField(params.num, state)),
RegField(params.num, state,
RegFieldDesc("state", "State: Example of a R/W Register with description.", reset = Some(0)))),
4 -> Seq(
RegField.w1ToClear(4, pending, state)))
RegField.w1ToClear(4, pending, state,
Some(RegFieldDesc("pending", "Pending: Example of a special (W1ToC) Register. " +
"Writing a bit here causes it to be reset to 0. " +
"The bits are set when the corresponding bit in 'state' is high.",
reset=Some(0xF)))))
)
}
// Create a concrete TL2 version of the abstract Example slave