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tilelink2: add a rightOR to go with our leftOR

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This commit is contained in:
Wesley W. Terpstra 2016-10-11 10:29:31 -07:00
parent b2a5d18e37
commit 4a975ca380
3 changed files with 12 additions and 4 deletions
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4
src/main/scala/uncore/tilelink2/AtomicAutomata.scala
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@ -138,8 +138,8 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
// Move the selected sign bit into the first byte position it will extend
val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0)
val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0)
val signext_a = FillInterleaved(8, highOR(signbit_a))
val signext_d = FillInterleaved(8, highOR(signbit_d))
val signext_a = FillInterleaved(8, leftOR(signbit_a))
val signext_d = FillInterleaved(8, leftOR(signbit_d))
// NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic
val wide_mask = FillInterleaved(8, mask)
val a_a_ext = (a_a & wide_mask) | signext_a

2
src/main/scala/uncore/tilelink2/Fuzzer.scala
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@ -17,7 +17,7 @@ class IDMapGenerator(numIds: Int) extends Module {
io.free.ready := Bool(true)
assert (!io.free.valid || !bitmap(io.free.bits)) // No double freeing
val select = ~(highOR(bitmap) << 1) & bitmap
val select = ~(leftOR(bitmap) << 1) & bitmap
io.alloc.bits := OHToUInt(select)
io.alloc.valid := bitmap.orR()

10
src/main/scala/uncore/tilelink2/package.scala
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@ -11,12 +11,20 @@ package object tilelink2
def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
def highOR(x: UInt) = {
// Fill 1s from low bits to high bits
def leftOR(x: UInt) = {
val w = x.getWidth
def helper(s: Int, x: UInt): UInt =
if (s >= w) x else helper(s+s, x | (x << s)(w-1,0))
helper(1, x)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt) = {
val w = x.getWidth
def helper(s: Int, x: UInt): UInt =
if (s >= w) x else helper(s+s, x | (x >> s))
helper(1, x)
}
// This gets used everywhere, so make the smallest circuit possible ...
def maskGen(addr_lo: UInt, lgSize: UInt, beatBytes: Int): UInt = {
val lgBytes = log2Ceil(beatBytes)