riscv/rocket-chip
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Fix +verbose flag for verilator

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This commit is contained in:
Andrew Waterman 2016-06-17 21:09:08 -07:00
parent 25ade44fe3
commit 4a8e6c773a
7 changed files with 20 additions and 12 deletions
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2
chisel3

@ -1 +1 @@
Subproject commit 07fa5622ccc995f925d6d967d2a386540c9064cc Subproject commit b5a534914795d9d17f4dfe623525f1b804e4c60f

9
csrc/emulator.cc
View File

@ -25,6 +25,8 @@
#include "emulator_type.h" #include "emulator_type.h"
htif_emulator_t* htif; htif_emulator_t* htif;
bool verbose;
void handle_sigterm(int sig) void handle_sigterm(int sig)
{ {
htif->stop(); htif->stop();
@ -41,7 +43,6 @@ int main(int argc, char** argv)
const char* loadmem = NULL; const char* loadmem = NULL;
FILE *vcdfile = NULL; FILE *vcdfile = NULL;
bool dramsim2 = false; bool dramsim2 = false;
bool log = false;
bool print_cycles = false; bool print_cycles = false;
uint64_t memsz_mb = MEM_SIZE / (1024*1024); uint64_t memsz_mb = MEM_SIZE / (1024*1024);
mm_t *mm[N_MEM_CHANNELS]; mm_t *mm[N_MEM_CHANNELS];
@ -58,7 +59,7 @@ int main(int argc, char** argv)
else if (arg == "+dramsim") else if (arg == "+dramsim")
dramsim2 = true; dramsim2 = true;
else if (arg == "+verbose") else if (arg == "+verbose")
log = true; verbose = true;
else if (arg.substr(0, 12) == "+max-cycles=") else if (arg.substr(0, 12) == "+max-cycles=")
max_cycles = atoll(argv[i]+12); max_cycles = atoll(argv[i]+12);
else if (arg.substr(0, 9) == "+loadmem=") else if (arg.substr(0, 9) == "+loadmem=")
@ -304,7 +305,7 @@ int main(int argc, char** argv)
tile.Top__io_host_out_ready = LIT<1>(1); tile.Top__io_host_out_ready = LIT<1>(1);
} }
if (log && (trace_count >> 1) >= start) if (verbose && (trace_count >> 1) >= start)
tile.print(stderr); tile.print(stderr);
// make sure we dump on cycle 0 to get dump_init // make sure we dump on cycle 0 to get dump_init
@ -356,7 +357,7 @@ int main(int argc, char** argv)
fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count >> 1); fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count >> 1);
ret = 2; ret = 2;
} }
else if (log || print_cycles) else if (verbose || print_cycles)
{ {
fprintf(stderr, "Completed after %ld cycles\n", trace_count >> 1); fprintf(stderr, "Completed after %ld cycles\n", trace_count >> 1);
} }

6
csrc/verilator.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef _ROCKET_VERILATOR_H
#define _ROCKET_VERILATOR_H
extern bool verbose;
#endif

9
emulator/Makefrag-verilator
View File

@ -56,8 +56,9 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
# Run Verilator to produce a fast binary to emulate this circuit. # Run Verilator to produce a fast binary to emulate this circuit.
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=$(MODEL).reset --assert \ VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \
-Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT -Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT \
-CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS))) cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
@ -73,12 +74,12 @@ $(emu): $(verilog) $(cppfiles) libdramsim.a $(consts_header) $(INSTALLED_VERILAT
mkdir -p $(generated_dir)/$(MODEL).$(CONFIG) mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \ -o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "$(CXXFLAGS) -DVERILATOR -I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)" -CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)"
$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk $(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
$(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR) $(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG) mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \ -o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "$(CXXFLAGS) -DVERILATOR -I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)" -CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)"
$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk $(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk

2
firrtl

@ -1 +1 @@
Subproject commit cc4e7e39ebad106ff72f7ac97dcdc99048ee5347 Subproject commit 860b04eff7758c3efae09fb0b5b908abad3b4593

2
riscv-tools

@ -1 +1 @@
Subproject commit 6748487730cbac62122a26aa11f458b7c1495f63 Subproject commit ba7efc42d04bcd1dacd8545acba58894aacc8c9e

2
rocket

@ -1 +1 @@
Subproject commit 2791b6c446c13c0b6663177269024cfa8a4c6c26 Subproject commit 94096e83ed58f2afaacdeb99ed2d885e3589d3f6