riscv/rocket-chip
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connect testharness components via member functions (#236)

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to prevent code duplication for new testbenches
This commit is contained in:
Yunsup Lee
2016-09-01 18:38:39 -07:00
committed by Andrew Waterman
parent 08089f695d
commit 4a7972be31
6 changed files with 51 additions and 52 deletions
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6
vsim/Makefrag
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@ -5,13 +5,13 @@
# Verilog sources
bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
$(base_dir)/vsrc/jtag_vpi.v \
$(base_dir)/vsrc/AsyncMailbox.v
$(base_dir)/vsrc/jtag_vpi.v \
$(base_dir)/vsrc/AsyncMailbox.v
sim_vsrcs = \
$(generated_dir)/$(MODEL).$(CONFIG).v \
$(generated_dir)/consts.$(CONFIG).vh \
$(base_dir)/vsrc/$(TB).v \
$(base_dir)/vsrc/$(TB).v \
$(base_dir)/vsrc/SimDTM.v \
$(bb_vsrcs)