From 4a401fc480f7fa3c5c4e0ebb895adfcd40c502cf Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 31 Aug 2016 15:53:25 -0700
Subject: [PATCH] tilelink2: add a Buffer adapter to insert pipeline stages

---
 uncore/src/main/scala/tilelink2/Buffer.scala | 30 ++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 uncore/src/main/scala/tilelink2/Buffer.scala

diff --git a/uncore/src/main/scala/tilelink2/Buffer.scala b/uncore/src/main/scala/tilelink2/Buffer.scala
new file mode 100644
index 00000000..dd749d9e
--- /dev/null
+++ b/uncore/src/main/scala/tilelink2/Buffer.scala
@@ -0,0 +1,30 @@
+// See LICENSE for license details.
+
+package uncore.tilelink2
+
+import Chisel._
+
+class TLBuffer(entries: Int = 2, pipe: Boolean = false) extends LazyModule
+{
+  val node = TLIdentityNode()
+
+  lazy val module = Module(new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in  = node.bundleIn
+      val out = node.bundleOut
+    }
+
+    val in  = io.in(0)
+    val out = io.out(0)
+
+    out.a <> Queue(in .a, entries, pipe)
+    in .d <> Queue(out.d, entries, pipe)
+    
+    val edge = node.edgesOut(0) // same as edgeIn(0)
+    if (edge.manager.anySupportAcquire && edge.client.anySupportProbe) {
+      in .b <> Queue(out.b, entries, pipe)
+      out.c <> Queue(in .c, entries, pipe)
+      out.e <> Queue(out.e, entries, pipe)
+    }
+  })
+}