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coreplex: make 'mem' port an Option until we can use a Seq

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Wesley W. Terpstra 2016-11-04 12:14:28 -07:00 committed by Henry Cook
parent 8f757a9135
commit 4a2cf6431b
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/coreplex/BaseCoreplex.scala
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@ -103,7 +103,7 @@ trait BankedL2CoherenceManagers {
def l2ManagerFactory(): (TLInwardNode, TLOutwardNode) def l2ManagerFactory(): (TLInwardNode, TLOutwardNode)
val l2Channels = Seq.fill(nMemChannels) { val mem = Seq.fill(nMemChannels) {
val bankBar = LazyModule(new TLXbar) val bankBar = LazyModule(new TLXbar)
val output = TLOutputNode() val output = TLOutputNode()
@ -124,8 +124,8 @@ trait BankedL2CoherenceManagersBundle {
val outer: BankedL2CoherenceManagers val outer: BankedL2CoherenceManagers
} => } =>
require (nMemChannels == 1, "Seq in Chisel Bundle needed to support > 1") // !!! require (nMemChannels <= 1, "Seq in Chisel Bundle needed to support > 1") // !!!
val mem = outer.l2Channels.map(_.bundleOut).toList.head // .head should be removed !!! val mem = outer.mem.map(_.bundleOut).toList.headOption // .headOption should be removed !!!
} }
trait BankedL2CoherenceManagersModule { trait BankedL2CoherenceManagersModule {