From 49c6b1ad1c589e9c2f2fc5e4f33c33746da2cb09 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 19 Nov 2015 00:15:36 -0800 Subject: [PATCH] add CacheFillTest --- groundtest/src/main/scala/cachetest.scala | 43 +++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 groundtest/src/main/scala/cachetest.scala diff --git a/groundtest/src/main/scala/cachetest.scala b/groundtest/src/main/scala/cachetest.scala new file mode 100644 index 00000000..f943a94b --- /dev/null +++ b/groundtest/src/main/scala/cachetest.scala @@ -0,0 +1,43 @@ +package groundtest + +import Chisel._ +import uncore._ +import cde.{Parameters, Field} + +class CacheFillTest(implicit val p: Parameters) extends GroundTest()(p) + with HasTileLinkParameters { + val capacityKb: Int = p("L2_CAPACITY_IN_KB") + val nblocks = capacityKb * 1024 / p(CacheBlockBytes) + val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4) + val state = Reg(init = s_start) + + val inflight = Reg(init = Bool(false)) + val active = state === s_prefetch || state === s_retrieve + + val (xact_id, xact_flip) = Counter(io.mem.acquire.fire(), tlMaxClientXacts) + val (req_block, round_done) = Counter(io.mem.acquire.fire(), nblocks) + + io.mem.acquire.valid := active && !inflight + io.mem.acquire.bits := Mux(state === s_prefetch, + GetPrefetch(xact_id, req_block), + GetBlock(xact_id, req_block)) + io.mem.grant.ready := active + + when (io.mem.acquire.fire()) { + inflight := Bool(true) + } + + val last_grant = !io.mem.grant.bits.hasMultibeatData() || + io.mem.grant.bits.addr_beat === UInt(tlDataBeats - 1) + + when (io.mem.grant.fire() && last_grant) { + inflight := Bool(false) + } + + when (state === s_start) { state := s_prefetch } + when (state === s_prefetch && round_done) { state := s_retrieve } + when (state === s_retrieve && round_done) { state := s_finished } + + io.finished := (state === s_finished) + io.cache.req.valid := Bool(false) +}