diff --git a/src/main/scala/devices/tilelink/BusBlocker.scala b/src/main/scala/devices/tilelink/BusBlocker.scala
index ae853c6b..dbf4314a 100644
--- a/src/main/scala/devices/tilelink/BusBlocker.scala
+++ b/src/main/scala/devices/tilelink/BusBlocker.scala
@@ -16,6 +16,7 @@ case class BusBlockerParams(
   pmpRegisters:     Int)
 {
   val page = 4096
+  val pageBits = log2Ceil(page)
   val size = (((pmpRegisters * 8) + page - 1) / page) * page
 
   require (pmpRegisters > 0)
@@ -25,28 +26,29 @@ case class BusBlockerParams(
   require (deviceBeatBytes  > 0 && isPow2(deviceBeatBytes))
 }
 
-case class DevicePMPParams(addressBits: Int)
+case class DevicePMPParams(addressBits: Int, pageBits: Int)
 class DevicePMP(params: DevicePMPParams) extends GenericParameterizedBundle(params)
 {
-  require (params.addressBits > 12)
+  require (params.addressBits > params.pageBits)
 
   val l = UInt(width = 1) // locked
   val a = UInt(width = 1) // LSB of A (0=disabled, 1=TOR)
   val r = UInt(width = 1)
   val w = UInt(width = 1)
 
-  val addr_hi = UInt(width = params.addressBits-12)
-  def address = Cat(addr_hi, UInt(0, width=12))
+  val addr_hi = UInt(width = params.addressBits-params.pageBits)
+  def address = Cat(addr_hi, UInt(0, width=params.pageBits))
+  def blockPriorAddress = l(0) && a(0)
 
-  def fields(locked: Bool): Seq[RegField] = {
-    def field(bits: Int, reg: UInt) =
+  def fields(blockAddress: Bool): Seq[RegField] = {
+    def field(bits: Int, reg: UInt, lock: Bool = l(0)) =
       RegField(bits, RegReadFn(reg), RegWriteFn((wen, data) => {
-        when (wen && !locked) { reg := data }
+        when (wen && !lock) { reg := data }
         Bool(true)
       }))
     Seq(
       RegField(10),
-      field(params.addressBits-12, addr_hi),
+      field(params.addressBits-params.pageBits, addr_hi, l(0) || blockAddress),
       RegField(56 - (params.addressBits-2)),
       field(1, r),
       field(1, w),
@@ -59,8 +61,8 @@ class DevicePMP(params: DevicePMPParams) extends GenericParameterizedBundle(para
 
 object DevicePMP
 {
-  def apply(addressBits: Int) = {
-    val out = Wire(new DevicePMP(DevicePMPParams(addressBits)))
+  def apply(addressBits: Int, pageBits: Int) = {
+    val out = Wire(new DevicePMP(DevicePMPParams(addressBits, pageBits)))
     out.l := UInt(0)
     out.a := UInt(0)
     out.r := UInt(0)
@@ -87,9 +89,9 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
 
     // We need to be able to represent +1 larger than the largest populated address
     val addressBits = log2Ceil(nodeOut.edgesOut(0).manager.maxAddress+1+1)
-    val pmps = RegInit(Vec.fill(params.pmpRegisters) { DevicePMP(addressBits) })
-    val locks = (pmps.map(_.l) zip (UInt(0) +: pmps.map(_.l))) map { case (x, n) => x | n }
-    controlNode.regmap(0 -> (pmps zip locks).map { case (p, l) => p.fields(l(0)) }.toList.flatten)
+    val pmps = RegInit(Vec.fill(params.pmpRegisters) { DevicePMP(addressBits, params.pageBits) })
+    val blocks = pmps.tail.map(_.blockPriorAddress) :+ Bool(false)
+    controlNode.regmap(0 -> (pmps zip blocks).map { case (p, b) => p.fields(b) }.toList.flatten)
 
     val in = io.in(0)
     val edge = nodeIn.edgesIn(0)
@@ -97,8 +99,8 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
     // Determine if a request is allowed
     val needW = in.a.bits.opcode =/= TLMessages.Get
     val needR = in.a.bits.opcode =/= TLMessages.PutFullData && in.a.bits.opcode =/= TLMessages.PutPartialData
-    val lte = Bool(false) +: pmps.map(in.a.bits.address < _.address)
-    val sel = (pmps.map(_.a) zip (lte.init zip lte.tail)) map { case (a, (l, r)) => a(0) && !l && r }
+    val lt = Bool(false) +: pmps.map(in.a.bits.address < _.address)
+    val sel = (pmps.map(_.a) zip (lt.init zip lt.tail)) map { case (a, (l, r)) => a(0) && !l && r }
     val ok = pmps.map(p => (p.r(0) || !needR) && (p.w(0) || !needW))
     val allow = PriorityMux(sel :+ Bool(true), ok :+ Bool(false)) // no match => deny