riscv/rocket-chip
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automatically infer MEM_TAG_BITS

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Andrew Waterman 2012-03-06 15:49:28 -08:00
parent 6e16b04ada
commit 499c5b4a2e
1 changed files with 1 additions and 2 deletions
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rocket/src/main/scala/consts.scala
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@ -217,10 +217,9 @@ object Constants
val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS) val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS)
// external memory interface // external memory interface
val MEM_TAG_BITS = if (HAVE_VEC) 5 else 4 val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)
val MEM_DATA_BITS = 128 val MEM_DATA_BITS = 128
val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
require(MEM_TAG_BITS >= max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS))
val DTLB_ENTRIES = 8; val DTLB_ENTRIES = 8;
val ITLB_ENTRIES = 8; val ITLB_ENTRIES = 8;