riscv/rocket-chip
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merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer

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This commit is contained in:
Howard Mao
2016-09-13 11:24:05 -07:00
parent f363f5f709
commit 49863944c4
3 changed files with 22 additions and 27 deletions
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4
src/main/scala/rocketchip/Periphery.scala
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@ -179,7 +179,7 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
}
(io.mem_tl zip coreplex.io.master.mem) foreach { case (tl, mem) =>
tl <> ClientUncachedTileLinkEnqueuer(mem, 2)(outermostParams)
tl <> TileLinkEnqueuer(mem, 2)(outermostParams)
}
}
@ -229,7 +229,7 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
io.mmio_ahb(idx) <> PeripheryUtils.convertTLtoAHB(mmio_ports(i), atomics = true)(outermostMMIOParams)
} else if (mmio_tl_start <= i && i < mmio_tl_end) {
val idx = i-mmio_tl_start
io.mmio_tl(idx) <> ClientUncachedTileLinkEnqueuer(mmio_ports(i), 2)(outermostMMIOParams)
io.mmio_tl(idx) <> TileLinkEnqueuer(mmio_ports(i), 2)(outermostMMIOParams)
} else {
require(false, "Unconnected external MMIO port")
}