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tilelink2: only accesses can have errors (release must make forward progress)

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This commit is contained in:
Wesley W. Terpstra 2016-08-22 15:36:39 -07:00
parent 6599bcb77b
commit 492a38aedc
2 changed files with 48 additions and 24 deletions
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33
uncore/src/main/scala/tilelink2/Bundles.scala
View File

@ -30,17 +30,23 @@ object TLMessages
val Hint = UInt(5) // . .
val AccessAck = UInt(0) // . .
val AccessAckData = UInt(1) // . .
val AccessAckError = UInt(2) // . .
val Acquire = UInt(6) // .
val Probe = UInt(6) // .
val ProbeAck = UInt(2) // .
val ProbeAckData = UInt(3) // .
val Release = UInt(4) // .
val ReleaseData = UInt(5) // .
//val PutThroughData = UInt(6) // . // future extension
val ReleaseAck = UInt(2) // .
val Grant = UInt(3) // .
val GrantData = UInt(4) // .
val ProbeAck = UInt(3) // .
val ProbeAckData = UInt(4) // .
val Release = UInt(5) // .
val ReleaseData = UInt(6) // .
//val PutThroughData = UInt(7) // . // future extension
val ReleaseAck = UInt(3) // .
val Grant = UInt(4) // .
val GrantData = UInt(5) // .
val GrantAck = UInt(0) // .
def isA(x: UInt) = x <= Acquire
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= GrantData
}
object TLPermissions
@ -49,25 +55,34 @@ object TLPermissions
val toT = UInt(0)
val toB = UInt(1)
val toN = UInt(2)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
val NtoB = UInt(0)
val NtoT = UInt(1)
val BtoT = UInt(2)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
val TtoB = UInt(0)
val TtoN = UInt(1)
val BtoN = UInt(2)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck)
val TtoT = UInt(3)
val BtoB = UInt(4)
val NtoN = UInt(5)
def isReport(x: UInt) = x <= NtoN
}
object TLAtomics
{
// Arithmetic types
def isArithmetic(x: UInt) = Bool(true)
// Logical types
def isLogical(x: UInt) = Bool(true)
}
class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params)
@ -100,7 +115,6 @@ class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params)
val source = UInt(width = params.sourceBits) // from
val address = UInt(width = params.addressBits) // to
val data = UInt(width = params.dataBits)
val error = Bool()
}
class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params)
@ -111,7 +125,6 @@ class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params)
val source = UInt(width = params.sourceBits) // to
val sink = UInt(width = params.sinkBits) // from
val data = UInt(width = params.dataBits)
val error = Bool()
}
class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params)

39
uncore/src/main/scala/tilelink2/Operations.scala
View File

@ -34,7 +34,6 @@ class TLEdgeOut(
c.source := fromSource
c.address := toAddress
c.data := UInt(0)
c.error := Bool(false)
(legal, c)
}
@ -48,7 +47,6 @@ class TLEdgeOut(
c.source := fromSource
c.address := toAddress
c.data := data
c.error := Bool(false)
(legal, c)
}
@ -60,7 +58,6 @@ class TLEdgeOut(
c.source := UInt(0)
c.address := toAddress
c.data := UInt(0)
c.error := Bool(false)
c
}
@ -72,7 +69,6 @@ class TLEdgeOut(
c.source := UInt(0)
c.address := toAddress
c.data := data
c.error := Bool(false)
c
}
@ -167,7 +163,7 @@ class TLEdgeOut(
(legal, a)
}
def AccessAck(toAddress: UInt, lgSize: UInt, error: Bool = Bool(false)) = {
def AccessAck(toAddress: UInt, lgSize: UInt) = {
val c = new TLBundleC(bundle)
c.opcode := TLMessages.AccessAck
c.param := UInt(0)
@ -175,7 +171,17 @@ class TLEdgeOut(
c.source := UInt(0)
c.address := toAddress
c.data := UInt(0)
c.error := error
c
}
def AccessAckError(toAddress: UInt, lgSize: UInt) = {
val c = new TLBundleC(bundle)
c.opcode := TLMessages.AccessAckError
c.param := UInt(0)
c.size := lgSize
c.source := UInt(0)
c.address := toAddress
c.data := UInt(0)
c
}
@ -187,7 +193,6 @@ class TLEdgeOut(
c.source := UInt(0)
c.address := toAddress
c.data := data
c.error := Bool(false)
c
}
}
@ -207,7 +212,7 @@ class TLEdgeIn(
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.wmask := fullMask(fromAddress, lgSize)
b.wmask := SInt(-1).asUInt
b.data := UInt(0)
(legal, b)
}
@ -220,7 +225,6 @@ class TLEdgeIn(
d.source := toSource
d.sink := fromSink
d.data := UInt(0)
d.error := Bool(false)
d
}
@ -232,7 +236,6 @@ class TLEdgeIn(
d.source := toSource
d.sink := fromSink
d.data := data
d.error := Bool(false)
d
}
@ -244,7 +247,6 @@ class TLEdgeIn(
d.source := toSource
d.sink := UInt(0)
d.data := UInt(0)
d.error := Bool(false)
d
}
@ -333,7 +335,7 @@ class TLEdgeIn(
(legal, b)
}
def AccessAck(toSource: UInt, lgSize: UInt, error: Bool = Bool(false)) = {
def AccessAck(toSource: UInt, lgSize: UInt) = {
val d = new TLBundleD(bundle)
d.opcode := TLMessages.AccessAck
d.param := UInt(0)
@ -341,7 +343,17 @@ class TLEdgeIn(
d.source := toSource
d.sink := UInt(0)
d.data := UInt(0)
d.error := error
d
}
def AccessAckError(toSource: UInt, lgSize: UInt) = {
val d = new TLBundleD(bundle)
d.opcode := TLMessages.AccessAckError
d.param := UInt(0)
d.size := lgSize
d.source := toSource
d.sink := UInt(0)
d.data := UInt(0)
d
}
@ -353,7 +365,6 @@ class TLEdgeIn(
d.source := toSource
d.sink := UInt(0)
d.data := data
d.error := Bool(false)
d
}
}