From 491184a8f809c7b6dc92a5cd7ff9d0ee2099f4a3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 30 Apr 2016 17:32:51 -0700 Subject: [PATCH] ERET -> xRET; remove mcfgaddr --- rocket/src/main/scala/csr.scala | 8 +++----- rocket/src/main/scala/idecode.scala | 1 + rocket/src/main/scala/instructions.scala | 22 ++++++++-------------- 3 files changed, 12 insertions(+), 19 deletions(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index edb8dc4f..86901dcd 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -222,7 +222,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) CSRs.misa -> UInt(isa), CSRs.mstatus -> read_mstatus, CSRs.mtvec -> reg_mtvec, - CSRs.mcfgaddr -> UInt(addrMap("io:int:configstring").start), CSRs.mipi -> reg_mip.msip, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, @@ -334,10 +333,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) Mux(insn_call, reg_mstatus.prv + Causes.user_ecall, Mux[UInt](insn_break, Causes.breakpoint, Causes.illegal_instruction))) val cause_lsbs = cause(log2Up(xLen)-1,0) - val can_delegate = Bool(p(UseVM)) && reg_mstatus.prv < PRV.M - val delegate = can_delegate && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs)) + val delegate = Bool(p(UseVM)) && reg_mstatus.prv < PRV.M && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs)) val tvec = Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec) - val epc = Mux(can_delegate, reg_sepc, reg_mepc) + val epc = Mux(Bool(p(UseVM)) && !csr_addr_priv(1), reg_sepc, reg_mepc) io.fatc := insn_sfence_vm io.evec := Mux(io.exception || csr_xcpt, tvec, epc) io.ptbr := reg_sptbr @@ -383,7 +381,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) } when (insn_ret) { - when (can_delegate) { + when (Bool(p(UseVM)) && !csr_addr_priv(1)) { when (reg_mstatus.spp.toBool) { reg_mstatus.sie := reg_mstatus.spie } reg_mstatus.spie := false reg_mstatus.spp := PRV.U diff --git a/rocket/src/main/scala/idecode.scala b/rocket/src/main/scala/idecode.scala index 107de8d6..c301424c 100644 --- a/rocket/src/main/scala/idecode.scala +++ b/rocket/src/main/scala/idecode.scala @@ -175,6 +175,7 @@ class XDecode(implicit val p: Parameters) extends DecodeConstants SCALL-> List(Y, N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N), SBREAK-> List(Y, N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N), SRET-> List(Y, N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N), + MRET-> List(Y, N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N), WFI-> List(Y, N,N,N,N,N,N,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.I,N,N,N), CSRRW-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.W,N,N,N), CSRRS-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.S,N,N,N), diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index 84b0ed70..808505d5 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -92,9 +92,12 @@ object Instructions { def AMOSWAP_D = BitPat("b00001????????????011?????0101111") def LR_D = BitPat("b00010??00000?????011?????0101111") def SC_D = BitPat("b00011????????????011?????0101111") - def SCALL = BitPat("b00000000000000000000000001110011") - def SBREAK = BitPat("b00000000000100000000000001110011") + def ECALL = BitPat("b00000000000000000000000001110011") + def EBREAK = BitPat("b00000000000100000000000001110011") + def URET = BitPat("b00000000001000000000000001110011") def SRET = BitPat("b00010000001000000000000001110011") + def HRET = BitPat("b00100000001000000000000001110011") + def MRET = BitPat("b00110000001000000000000001110011") def SFENCE_VM = BitPat("b000100000100?????000000001110011") def WFI = BitPat("b00010000010100000000000001110011") def CSRRW = BitPat("b?????????????????001?????1110011") @@ -206,9 +209,8 @@ object Instructions { def RDCYCLEH = BitPat("b11001000000000000010?????1110011") def RDTIMEH = BitPat("b11001000000100000010?????1110011") def RDINSTRETH = BitPat("b11001000001000000010?????1110011") - def ECALL = BitPat("b00000000000000000000000001110011") - def EBREAK = BitPat("b00000000000100000000000001110011") - def ERET = BitPat("b00010000000000000000000001110011") + def SCALL = BitPat("b00000000000000000000000001110011") + def SBREAK = BitPat("b00000000000100000000000001110011") } object Causes { val misaligned_fetch = 0x0 @@ -265,7 +267,6 @@ object CSRs { val mideleg = 0x303 val mie = 0x304 val mtvec = 0x305 - val mtimecmp = 0x321 val mscratch = 0x340 val mepc = 0x341 val mcause = 0x342 @@ -287,15 +288,13 @@ object CSRs { val mvendorid = 0xf11 val marchid = 0xf12 val mimpid = 0xf13 - val mcfgaddr = 0xf14 - val mhartid = 0xf15 + val mhartid = 0xf14 val mtohost = 0x7c0 val mfromhost = 0x7c1 val mreset = 0x7c2 val cycleh = 0xc80 val timeh = 0xc81 val instreth = 0xc82 - val mtimecmph = 0x361 val mucycle_deltah = 0x780 val mutime_deltah = 0x781 val muinstret_deltah = 0x782 @@ -303,7 +302,6 @@ object CSRs { val mstime_deltah = 0x785 val msinstret_deltah = 0x786 val mcycleh = 0xf80 - val mtimeh = 0xf81 val minstreth = 0xf82 val all = { val res = collection.mutable.ArrayBuffer[Int]() @@ -331,7 +329,6 @@ object CSRs { res += mideleg res += mie res += mtvec - res += mtimecmp res += mscratch res += mepc res += mcause @@ -353,7 +350,6 @@ object CSRs { res += mvendorid res += marchid res += mimpid - res += mcfgaddr res += mhartid res += mtohost res += mfromhost @@ -365,7 +361,6 @@ object CSRs { res += cycleh res += timeh res += instreth - res += mtimecmph res += mucycle_deltah res += mutime_deltah res += muinstret_deltah @@ -373,7 +368,6 @@ object CSRs { res += mstime_deltah res += msinstret_deltah res += mcycleh - res += mtimeh res += minstreth res.toArray }