updated riscv-bmarks and riscv-tests to build with new toolchain
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@ -45,7 +45,7 @@ class rocketDpath extends Component
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val alu = new rocketDpathALU();
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val ex_alu_out = alu.io.out;
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val ex_jr_target = ex_alu_out(31,0);
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val ex_jr_target = ex_alu_out(VADDR_BITS,0);
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val div = new rocketDivider(64);
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val div_result = div.io.div_result_bits;
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@ -342,7 +342,7 @@ class rocketDpath extends Component
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// D$ request interface (registered inside D$ module)
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// other signals (req_val, req_rdy) connect to control module
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io.dmem.req_addr := ex_alu_out(PADDR_BITS-1,0);
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io.dmem.req_addr := ex_alu_out(VADDR_BITS-1,0);
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io.dmem.req_data := ex_reg_rs2;
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io.dmem.req_tag := ex_reg_waddr;
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