riscv/rocket-chip
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Merge branch 'master' into intbar

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Wesley W. Terpstra 2016-09-08 21:09:59 -07:00 committed by GitHub
commit 48ca478578
2 changed files with 1 additions and 1 deletions
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sbt-launch.jar
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src/main/scala/uncore/tilelink2/Legacy.scala
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@ -107,7 +107,7 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
out.a.bits.addr_hi := ~(~address | addressMask) >> log2Ceil(tlDataBytes) out.a.bits.addr_hi := ~(~address | addressMask) >> log2Ceil(tlDataBytes)
// TL legacy does not support bus errors // TL legacy does not support bus errors
assert (!out.d.bits.error) assert (!out.d.valid || !out.d.bits.error)
// Recreate the beat address counter // Recreate the beat address counter
val beatCounter = RegInit(UInt(0, width = tlBeatAddrBits)) val beatCounter = RegInit(UInt(0, width = tlBeatAddrBits))