riscv/rocket-chip
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Bump FIRRTL to instantiate Sequential Memory Macros

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Megan Wachs committed 2016-09-06 14:48:28 -07:00
1 parent 1fec9807f6
commit 48098f5e2d
4 files changed
+85 -57
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vsim/Makefrag
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@@ -10,6 +10,7 @@ bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
sim_vsrcs = \
$(generated_dir)/$(MODEL).$(CONFIG).v \
$(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v \
$(generated_dir)/consts.$(CONFIG).vh \
$(base_dir)/vsrc/$(TB).v \
$(base_dir)/vsrc/SimDTM.v \