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add CacheFillTest to check L2 conflict misses

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This commit is contained in:
Howard Mao
2015-11-19 00:16:28 -08:00
parent 3514b6eb87
commit 4806f72b08
2 changed files with 35 additions and 20 deletions
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2
groundtest

Submodule groundtest updated: cb4b70a820...e9112db2ca

53
src/main/scala/Configs.scala
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@@ -248,39 +248,54 @@ class WithZscale extends Config(
class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig) class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
class WithMemtest extends Config ( class WithGroundTest extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {
case TLKey("L1toL2") => case TLKey("L1toL2") =>
TileLinkParameters( TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)), coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels), nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
nCachingClients = site(NGeneratorTiles), nCachingClients = site(NTiles),
nCachelessClients = site(NGeneratorTiles) + 1, nCachelessClients = site(NTiles) + 1,
maxClientXacts = 1, maxClientXacts = 1,
maxClientsPerPort = site(NGeneratorsPerTile), maxClientsPerPort = site(GroundTestMaxXacts),
maxManagerXacts = site(NAcquireTransactors) + 2, maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8) dataBits = site(CacheBlockBytes)*8)
case BuildTiles => {
(0 until site(NTiles)).map { i =>
(r: Bool, p: Parameters) =>
Module(new GroundTestTile(i, r)
(p.alterPartial({case TLId => "L1toL2"})))
}
}
case GroundTestMaxXacts => 1
})
case NTiles => site(NGeneratorTiles) class WithMemtest extends Config(
(pname, site, here) => pname match {
case NGeneratorTiles => 1 case NGenerators => 1
case NGeneratorsPerTile => 1
case GenerateUncached => true case GenerateUncached => true
case GenerateCached => true case GenerateCached => true
case MaxGenerateRequests => 128 case MaxGenerateRequests => 128
case GeneratorStartAddress => 0 case GeneratorStartAddress => 0
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new GeneratorTest(id)(p))
case BuildTiles => { case NTiles => site(NGenerators)
(0 until site(NTiles)).map { i =>
(r: Bool, p: Parameters) => Module(
new GeneratorTile(i, r)
(p.alterPartial({case TLId => "L1toL2"})))
}
}
}) })
class MemtestConfig extends Config(new WithMemtest ++ new DefaultConfig) class WithCacheFillTest extends Config(
class MemtestL2Config extends Config(new WithMemtest ++ new DefaultL2Config) (pname, site, here) => pname match {
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new CacheFillTest()(p))
case "L2_CAPACITY_IN_KB" => 4
})
class GroundTestConfig extends Config(new WithGroundTest ++ new DefaultConfig)
class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
class MemtestL2Config extends Config(
new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
class CacheFillTestConfig extends Config(
new WithCacheFillTest ++ new WithL2Cache ++ new GroundTestConfig)
class FPGAConfig extends Config ( class FPGAConfig extends Config (
(pname,site,here) => pname match { (pname,site,here) => pname match {
@@ -326,7 +341,7 @@ class DualChannelDualBankL2Config extends Config(
class MemtestDualChannelDualBankL2Config extends Config( class MemtestDualChannelDualBankL2Config extends Config(
new With2MemoryChannels ++ new With2BanksPerMemChannel ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++
new WithMemtest ++ new WithL2Cache ++ new DefaultConfig) new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
class WithAccumulatorExample extends Config( class WithAccumulatorExample extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {