riscv/rocket-chip
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head should be working again

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This commit is contained in:
Daiwei Li 2012-02-26 00:30:50 -08:00
parent 569698b824
commit 47dbc2a417
1 changed files with 3 additions and 3 deletions
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6
rocket/src/main/scala/cpu.scala
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@ -37,7 +37,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
{ {
vu = new vu() vu = new vu()
// cpu, vector prefetch, and vector use the DTLB // cpu, vector prefetch, and vector use the DTLB
val dtlbarb = new cArbiter(3)({new ioDTLB_CPU_req()}) val dtlbarb = new rArbiter(3)({new ioDTLB_CPU_req()})
val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3))) val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen } when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
@ -204,8 +204,8 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
vu.io.vec_ackq.ready := ctrl.io.vec_iface.vackq_ready vu.io.vec_ackq.ready := ctrl.io.vec_iface.vackq_ready
// exceptions // exceptions
// dpath.io.vec_iface.eaddr vu.io.cpu_exception.addr := dpath.io.vec_iface.eaddr.toUFix
// dpath.io.vec_iface.exception vu.io.cpu_exception.exception := dpath.io.vec_iface.exception
// hooking up vector memory interface // hooking up vector memory interface
ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid