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Merge pull request #1251 from freechipsproject/rocket_covers

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Added functional covers
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bipult
2018-02-25 09:01:33 -08:00
committed by GitHub
parent 95294bbdcb 2e548c9ad2
commit 47d63d6baa
1 changed files with 27 additions and 0 deletions
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27
src/main/scala/tilelink/FIFOFixer.scala
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@@ -5,6 +5,8 @@ package freechips.rocketchip.tilelink
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
import scala.math.max
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
@@ -98,6 +100,31 @@ class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Para
out.c.valid := Bool(false)
out.e.valid := Bool(false)
}
//Functional cover properties
cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(UInt(0, width = edgeIn.client.endSourceId))
val SourceIdSet = Wire(init = UInt(0, width = edgeIn.client.endSourceId))
val SourceIdClear = Wire(init = UInt(0, width = edgeIn.client.endSourceId))
when (a_first && in.a.fire() && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire()) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}