diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala
index 78c354f8..8eab8e08 100644
--- a/src/main/scala/uncore/tilelink2/Edges.scala
+++ b/src/main/scala/uncore/tilelink2/Edges.scala
@@ -216,8 +216,12 @@ class TLEdge(
     x match {
       case _: TLBundleE => UInt(0)
       case bundle: TLDataChannel => {
-        val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
-        Mux(hasData(bundle), decode, UInt(0))
+        if (maxLgSize == 0) {
+          UInt(0)
+        } else {
+          val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
+          Mux(hasData(bundle), decode, UInt(0))
+        }
       }
     }
   }
diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala
index 0f41042b..e756614b 100644
--- a/src/main/scala/uncore/tilelink2/Parameters.scala
+++ b/src/main/scala/uncore/tilelink2/Parameters.scala
@@ -383,7 +383,7 @@ case class TLEdgeParameters(
   manager: TLManagerPortParameters)
 {
   val maxTransfer = max(client.maxTransfer, manager.maxTransfer)
-  val maxLgSize = log2Up(maxTransfer)
+  val maxLgSize = log2Ceil(maxTransfer)
 
   // Sanity check the link...
   require (maxTransfer >= manager.beatBytes)