riscv/rocket-chip
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fix meta hazard counter to reset on new meta writes

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This commit is contained in:
Andrew Waterman 2013-05-01 16:35:24 -07:00
parent a6a88fce19
commit 474d321cc7
1 changed files with 2 additions and 1 deletions
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3
rocket/src/main/scala/nbdcache.scala
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@ -285,7 +285,8 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
val meta_hazard = Reg(resetVal = UFix(0,2)) val meta_hazard = Reg(resetVal = UFix(0,2))
when (meta_hazard != 0 || io.meta_write.fire()) { meta_hazard := meta_hazard + 1 } when (meta_hazard != 0) { meta_hazard := meta_hazard + 1 }
when (io.meta_write.fire()) { meta_hazard := 1 }
io.probe_rdy := !idx_match || (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && meta_hazard === 0) io.probe_rdy := !idx_match || (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && meta_hazard === 0)
io.meta_write.valid := state === s_meta_write_req || state === s_meta_clear io.meta_write.valid := state === s_meta_write_req || state === s_meta_clear