riscv/rocket-chip
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New address map

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This commit is contained in:
Andrew Waterman 2016-04-30 20:59:36 -07:00
parent d0aa4c722d
commit 46bbbba5e6
11 changed files with 75 additions and 63 deletions
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7
csrc/emulator.cc
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@ -101,8 +101,7 @@ int main(int argc, char** argv)
} }
// Instantiate HTIF // Instantiate HTIF
htif = new htif_emulator_t(memsz_mb, htif = new htif_emulator_t(std::vector<std::string>(argv + 1, argv + argc));
std::vector<std::string>(argv + 1, argv + argc));
int htif_bits = tile.Top__io_host_in_bits.width(); int htif_bits = tile.Top__io_host_in_bits.width();
assert(htif_bits % 8 == 0 && htif_bits <= val_n_bits()); assert(htif_bits % 8 == 0 && htif_bits <= val_n_bits());
@ -181,13 +180,13 @@ int main(int argc, char** argv)
for (int i = 0; i < N_MEM_CHANNELS; i++) { for (int i = 0; i < N_MEM_CHANNELS; i++) {
mm[i]->tick( mm[i]->tick(
mem_ar_valid[i]->to_bool(), mem_ar_valid[i]->to_bool(),
mem_ar_bits_addr[i]->lo_word(), mem_ar_bits_addr[i]->lo_word() - MEM_BASE,
mem_ar_bits_id[i]->lo_word(), mem_ar_bits_id[i]->lo_word(),
mem_ar_bits_size[i]->lo_word(), mem_ar_bits_size[i]->lo_word(),
mem_ar_bits_len[i]->lo_word(), mem_ar_bits_len[i]->lo_word(),
mem_aw_valid[i]->to_bool(), mem_aw_valid[i]->to_bool(),
mem_aw_bits_addr[i]->lo_word(), mem_aw_bits_addr[i]->lo_word() - MEM_BASE,
mem_aw_bits_id[i]->lo_word(), mem_aw_bits_id[i]->lo_word(),
mem_aw_bits_size[i]->lo_word(), mem_aw_bits_size[i]->lo_word(),
mem_aw_bits_len[i]->lo_word(), mem_aw_bits_len[i]->lo_word(),

12
csrc/htif_emulator.h
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@ -10,12 +10,10 @@ class htif_emulator_t : public htif_pthread_t
int memory_channel_mux_select; int memory_channel_mux_select;
public: public:
htif_emulator_t(uint32_t memsz_mb, const std::vector<std::string>& args) htif_emulator_t(const std::vector<std::string>& args)
: htif_pthread_t(args), : htif_pthread_t(args),
memory_channel_mux_select(0) memory_channel_mux_select(0)
{ {
this->_memsz_mb = memsz_mb;
for (const auto& arg: args) { for (const auto& arg: args) {
if (!strncmp(arg.c_str(), "+memory_channel_mux_select=", 27)) if (!strncmp(arg.c_str(), "+memory_channel_mux_select=", 27))
memory_channel_mux_select = atoi(arg.c_str()+27); memory_channel_mux_select = atoi(arg.c_str()+27);
@ -36,14 +34,6 @@ class htif_emulator_t : public htif_pthread_t
set_clock_divisor(5, 2); set_clock_divisor(5, 2);
htif_pthread_t::start(); htif_pthread_t::start();
} }
uint32_t mem_mb() {
uint32_t scr_mb = htif_pthread_t::mem_mb();
return (_memsz_mb < scr_mb) ? _memsz_mb : scr_mb;
}
private:
uint32_t _memsz_mb;
}; };
#endif #endif

9
csrc/vcs_main.rocketTestHarness.cc
View File

@ -30,8 +30,6 @@ void htif_fini(vc_handle failure)
int main(int argc, char** argv) int main(int argc, char** argv)
{ {
unsigned long memsz_mb = MEM_SIZE / (1024*1024);
for (int i = 1; i < argc; i++) for (int i = 1; i < argc; i++)
{ {
if (!strcmp(argv[i], "+dramsim")) if (!strcmp(argv[i], "+dramsim"))
@ -42,8 +40,7 @@ int main(int argc, char** argv)
memory_channel_mux_select = atoi(argv[i]+27); memory_channel_mux_select = atoi(argv[i]+27);
} }
htif = new htif_emulator_t(memsz_mb, htif = new htif_emulator_t(std::vector<std::string>(argv + 1, argv + argc));
std::vector<std::string>(argv + 1, argv + argc));
for (int i=0; i<N_MEM_CHANNELS; i++) { for (int i=0; i<N_MEM_CHANNELS; i++) {
mm[i] = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t); mm[i] = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
@ -107,13 +104,13 @@ void memory_tick(
mmc->tick mmc->tick
( (
vc_getScalar(ar_valid), vc_getScalar(ar_valid),
vc_4stVectorRef(ar_addr)->d, vc_4stVectorRef(ar_addr)->d - MEM_BASE,
vc_4stVectorRef(ar_id)->d, vc_4stVectorRef(ar_id)->d,
vc_4stVectorRef(ar_size)->d, vc_4stVectorRef(ar_size)->d,
vc_4stVectorRef(ar_len)->d, vc_4stVectorRef(ar_len)->d,
vc_getScalar(aw_valid), vc_getScalar(aw_valid),
vc_4stVectorRef(aw_addr)->d, vc_4stVectorRef(aw_addr)->d - MEM_BASE,
vc_4stVectorRef(aw_id)->d, vc_4stVectorRef(aw_id)->d,
vc_4stVectorRef(aw_size)->d, vc_4stVectorRef(aw_size)->d,
vc_4stVectorRef(aw_len)->d, vc_4stVectorRef(aw_len)->d,

16
emulator/Makefile
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@ -74,19 +74,19 @@ ifneq ($(MAKECMDGOALS),clean)
-include $(generated_dir)/$(MODEL).$(CONFIG).d -include $(generated_dir)/$(MODEL).$(CONFIG).d
endif endif
$(output_dir)/%.run: $(output_dir)/%.hex emulator-$(MODEL)-$(CONFIG) $(output_dir)/%.run: $(output_dir)/% emulator-$(MODEL)-$(CONFIG)
./$(emu) +dramsim +max-cycles=$(timeout_cycles) +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] ./$(emu) +dramsim +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
$(output_dir)/%.out: $(output_dir)/%.hex emulator-$(MODEL)-$(CONFIG) $(output_dir)/%.out: $(output_dir)/% emulator-$(MODEL)-$(CONFIG)
./$(emu) +dramsim +max-cycles=$(timeout_cycles) +verbose +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ] ./$(emu) +dramsim +max-cycles=$(timeout_cycles) +verbose $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
$(output_dir)/%.vcd: $(output_dir)/%.hex emulator-$(MODEL)-$(CONFIG)-debug $(output_dir)/%.vcd: $(output_dir)/% emulator-$(MODEL)-$(CONFIG)-debug
./$(emu_debug) +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@ +loadmem=$< none $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] ./$(emu_debug) +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@ $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
$(output_dir)/%.vpd: $(output_dir)/%.hex emulator-$(MODEL)-$(CONFIG)-debug $(output_dir)/%.vpd: $(output_dir)/% emulator-$(MODEL)-$(CONFIG)-debug
rm -rf $@.vcd && mkfifo $@.vcd rm -rf $@.vcd && mkfifo $@.vcd
vcd2vpd $@.vcd $@ > /dev/null & vcd2vpd $@.vcd $@ > /dev/null &
./$(emu_debug) +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@.vcd +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] ./$(emu_debug) +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@.vcd $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
run: run-asm-tests run-bmark-tests run: run-asm-tests run-bmark-tests
run-debug: run-asm-tests-debug run-bmark-tests-debug run-debug: run-asm-tests-debug run-bmark-tests-debug

2
riscv-tools

@ -1 +1 @@
Subproject commit 34a245b943bcae60b6ccece8aba86670cd0f2631 Subproject commit 40a956a7a5335c051416a69eed7d28936b8d967a

2
rocket

@ -1 +1 @@
Subproject commit 4aca3088510183e344994ce0fc4206e95083a5a7 Subproject commit 8869c1a44aa91c303eb5ea2bf880e4d74806fce7

37
src/main/scala/Configs.scala
View File

@ -25,25 +25,32 @@ class DefaultConfig extends Config (
type PF = PartialFunction[Any,Any] type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
lazy val internalIOAddrMap: AddrMap = { lazy val internalIOAddrMap: AddrMap = {
val deviceTree = AddrMapEntry("configstring", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.R))) val debugModule = AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
val bootROM = AddrMapEntry("bootrom", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.RX)))
val rtc = AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW))) val rtc = AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
new AddrMap(Seq(deviceTree, rtc)) new AddrMap(Seq(debugModule, bootROM, rtc))
} }
lazy val globalAddrMap: AddrMap = { lazy val (globalAddrMap, globalAddrHashMap) = {
val memSize = 1L << 30 val memSize = 1L << 31
val memAlign = 1L << 31 val memAlign = 1L << 30
val extIOSize = 1L << 29 val extIOSize = 1L << 30
val mem = MemSize(memSize, memAlign, MemAttr(AddrMapProt.RWX, true)) val mem = MemSize(memSize, memAlign, MemAttr(AddrMapProt.RWX, true))
val io = AddrMap( val io = AddrMap(
AddrMapEntry("int", MemSubmap(internalIOAddrMap.computeSize, internalIOAddrMap)), AddrMapEntry("int", MemSubmap(internalIOAddrMap.computeSize, internalIOAddrMap)),
AddrMapEntry("ext", MemSize(extIOSize, extIOSize, MemAttr(AddrMapProt.RWX)))) AddrMapEntry("ext", MemSize(extIOSize, extIOSize, MemAttr(AddrMapProt.RWX))))
val addrMap = AddrMap(
AddrMapEntry("io", MemSubmap(io.computeSize, io)),
AddrMapEntry("mem", mem))
val addrHashMap = new AddrHashMap(addrMap)
Dump("MEM_BASE", addrHashMap("mem").start)
Dump("MEM_SIZE", memSize) Dump("MEM_SIZE", memSize)
AddrMap( Dump("IO_BASE", addrHashMap("io:ext").start)
AddrMapEntry("mem", mem), Dump("IO_SIZE", extIOSize)
AddrMapEntry("io", MemSubmap(io.computeSize, io))) (addrMap, addrHashMap)
} }
def makeConfigString() = { def makeConfigString() = {
val addrMap = new AddrHashMap(globalAddrMap) val addrMap = globalAddrHashMap
val xLen = site(XLen) val xLen = site(XLen)
val res = new StringBuilder val res = new StringBuilder
res append "platform {\n" res append "platform {\n"
@ -155,7 +162,7 @@ class DefaultConfig extends Config (
if (site(XLen) == 64) (rv64i, rv64u) if (site(XLen) == 64) (rv64i, rv64u)
else (rv32i, rv32u) else (rv32i, rv32u)
TestGeneration.addSuites(rvi.map(_("p"))) TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rvu.map(_(env)))) TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(bmarks) TestGeneration.addSuite(bmarks)
List.fill(site(NTiles)){ (r: Bool, p: Parameters) => List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"}))) Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
@ -178,7 +185,7 @@ class DefaultConfig extends Config (
case FastMulDiv => true case FastMulDiv => true
case XLen => 64 case XLen => 64
case UseFPU => { case UseFPU => {
val env = if(site(UseVM)) List("p","pt","v") else List("p","pt") val env = if(site(UseVM)) List("p","v") else List("p")
if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf)) if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
else TestGeneration.addSuites(env.map(rv64ufNoDiv)) else TestGeneration.addSuites(env.map(rv64ufNoDiv))
true true
@ -189,9 +196,9 @@ class DefaultConfig extends Config (
case CoreInstBits => 32 case CoreInstBits => 32
case CoreDataBits => site(XLen) case CoreDataBits => site(XLen)
case NCustomMRWCSRs => 0 case NCustomMRWCSRs => 0
case ResetVector => BigInt(0x0) case ResetVector => BigInt(0x1000)
case MtvecInit => BigInt(0x8) case MtvecInit => BigInt(0x1010)
case MtvecWritable => false case MtvecWritable => true
//Uncore Paramters //Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients

29
src/main/scala/RocketChip.scala
View File

@ -93,6 +93,27 @@ object TopUtils {
conv.io.tl <> tl conv.io.tl <> tl
TopUtils.connectNasti(nasti, conv.io.nasti) TopUtils.connectNasti(nasti, conv.io.nasti)
} }
def makeBootROM()(implicit p: Parameters) = {
val rom = java.nio.ByteBuffer.allocate(32)
rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
// for now, have the reset vector jump straight to memory
val addrHashMap = new AddrHashMap(p(GlobalAddrMap))
val resetToMemDist = addrHashMap("mem").start - p(ResetVector)
require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
val configStringAddr = p(ResetVector).toInt + rom.capacity
rom.putInt(0x00000297 + resetToMemDist.toInt) // auipc t0, &mem - &here
rom.putInt(0x00028067) // jr t0
rom.putInt(0) // reserved
rom.putInt(configStringAddr) // pointer to config string
rom.putInt(0) // default trap vector
rom.putInt(0) // ...
rom.putInt(0) // ...
rom.putInt(0) // ...
rom.array() ++ p(ConfigString).toSeq
}
} }
/** Top-level module for the chip */ /** Top-level module for the chip */
@ -165,8 +186,6 @@ class Uncore(implicit val p: Parameters) extends Module
val addrHashMap = new AddrHashMap(addrMap) val addrHashMap = new AddrHashMap(addrMap)
val scrFile = Module(new SCRFile("UNCORE_SCR", 0)) val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
scrFile.io.smi <> htif.io.scr scrFile.io.smi <> htif.io.scr
scrFile.io.scr.attach(Wire(init = UInt(nTiles)), "N_CORES")
scrFile.io.scr.attach(Wire(init = UInt(addrHashMap("io:int:configstring").start >> 20)), "MMIO_BASE")
// scrFile.io.scr <> (... your SCR connections ...) // scrFile.io.scr <> (... your SCR connections ...)
buildMMIONetwork(p.alterPartial({case TLId => "MMIO_Outermost"})) buildMMIONetwork(p.alterPartial({case TLId => "MMIO_Outermost"}))
@ -195,9 +214,9 @@ class Uncore(implicit val p: Parameters) extends Module
rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port) rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port)
io.timerIRQs := rtc.io.irqs io.timerIRQs := rtc.io.irqs
val deviceTree = Module(new ROMSlave(p(ConfigString).toSeq)) val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
val deviceTreeAddr = ioAddrHashMap("int:configstring") val bootROMAddr = ioAddrHashMap("int:bootrom")
deviceTree.io <> mmioNetwork.io.out(deviceTreeAddr.port) bootROM.io <> mmioNetwork.io.out(bootROMAddr.port)
TopUtils.connectTilelinkNasti(io.mmio, mmioNetwork.io.out(ioAddrHashMap("ext").port)) TopUtils.connectTilelinkNasti(io.mmio, mmioNetwork.io.out(ioAddrHashMap("ext").port))
} }

2
src/main/scala/Testing.scala
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@ -140,7 +140,7 @@ object DefaultTestSuites {
val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi") val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_) val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_)
val rv32miNames = LinkedHashSet("csr", "mcsr", "wfi", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall", "timer") val rv32miNames = LinkedHashSet("csr", "mcsr", "wfi", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_) val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
val rv32u = List(rv32ui, rv32um, rv32ua) val rv32u = List(rv32ui, rv32um, rv32ua)

2
uncore

@ -1 +1 @@
Subproject commit c57928fad82beb9e7cab82cb03cf394b24512351 Subproject commit 0b3199d3ae19aafe05d723d63c1991d57330f1ab

20
vsim/Makefrag-verilog
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@ -46,20 +46,20 @@ $(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
$(sim_dir)/dramsim2_ini: $(sim_dir)/dramsim2_ini:
ln -s $(base_dir)/emulator/dramsim2_ini $(sim_dir)/dramsim2_ini ln -s $(base_dir)/emulator/dramsim2_ini $(sim_dir)/dramsim2_ini
$(output_dir)/%.run: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv) $(output_dir)/%.run: $(output_dir)/% $(sim_dir)/dramsim2_ini $(simv)
cd $(sim_dir) && $(exec_simv) +dramsim +verbose +max-cycles=$(timeout_cycles) +loadmem=$< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] cd $(sim_dir) && $(exec_simv) +dramsim +verbose +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
$(output_dir)/%.out: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv) $(output_dir)/%.out: $(output_dir)/% $(sim_dir)/dramsim2_ini $(simv)
cd $(sim_dir) && $(exec_simv) +dramsim +verbose +max-cycles=$(timeout_cycles) +loadmem=$< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ] cd $(sim_dir) && $(exec_simv) +dramsim +verbose +max-cycles=$(timeout_cycles) $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
$(output_dir)/%.vcd: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv_debug) $(output_dir)/%.vcd: $(output_dir)/% $(sim_dir)/dramsim2_ini $(simv_debug)
cd $(sim_dir) && $(exec_simv_debug) +dramsim +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) +loadmem=$< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] cd $(sim_dir) && $(exec_simv_debug) +dramsim +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
$(output_dir)/%.vpd: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv_debug) $(output_dir)/%.vpd: $(output_dir)/% $(sim_dir)/dramsim2_ini $(simv_debug)
cd $(sim_dir) && $(exec_simv_debug) +dramsim +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) +loadmem=$< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] cd $(sim_dir) && $(exec_simv_debug) +dramsim +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
$(output_dir)/%.saif: $(output_dir)/%.hex $(sim_dir)/dramsim2_ini $(simv_debug) $(output_dir)/%.saif: $(output_dir)/% $(sim_dir)/dramsim2_ini $(simv_debug)
cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +dramsim +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) +loadmem=$<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1 cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +dramsim +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1
run: run-asm-tests run-bmark-tests run: run-asm-tests run-bmark-tests
run-debug: run-asm-tests-debug run-bmark-tests-debug run-debug: run-asm-tests-debug run-bmark-tests-debug