New address map
This commit is contained in:
Andrew Waterman
@ -25,25 +25,32 @@ class DefaultConfig extends Config (
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val internalIOAddrMap: AddrMap = {
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val deviceTree = AddrMapEntry("configstring", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.R)))
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val debugModule = AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
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val bootROM = AddrMapEntry("bootrom", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.RX)))
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val rtc = AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
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new AddrMap(Seq(deviceTree, rtc))
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new AddrMap(Seq(debugModule, bootROM, rtc))
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}
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lazy val globalAddrMap: AddrMap = {
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val memSize = 1L << 30
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val memAlign = 1L << 31
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val extIOSize = 1L << 29
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lazy val (globalAddrMap, globalAddrHashMap) = {
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val memSize = 1L << 31
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val memAlign = 1L << 30
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val extIOSize = 1L << 30
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val mem = MemSize(memSize, memAlign, MemAttr(AddrMapProt.RWX, true))
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val io = AddrMap(
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AddrMapEntry("int", MemSubmap(internalIOAddrMap.computeSize, internalIOAddrMap)),
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AddrMapEntry("ext", MemSize(extIOSize, extIOSize, MemAttr(AddrMapProt.RWX))))
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val addrMap = AddrMap(
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AddrMapEntry("io", MemSubmap(io.computeSize, io)),
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AddrMapEntry("mem", mem))
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val addrHashMap = new AddrHashMap(addrMap)
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Dump("MEM_BASE", addrHashMap("mem").start)
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Dump("MEM_SIZE", memSize)
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AddrMap(
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AddrMapEntry("mem", mem),
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AddrMapEntry("io", MemSubmap(io.computeSize, io)))
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Dump("IO_BASE", addrHashMap("io:ext").start)
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Dump("IO_SIZE", extIOSize)
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(addrMap, addrHashMap)
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}
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def makeConfigString() = {
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val addrMap = new AddrHashMap(globalAddrMap)
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val addrMap = globalAddrHashMap
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val xLen = site(XLen)
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val res = new StringBuilder
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res append "platform {\n"
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@ -155,7 +162,7 @@ class DefaultConfig extends Config (
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if (site(XLen) == 64) (rv64i, rv64u)
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else (rv32i, rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(bmarks)
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
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@ -178,7 +185,7 @@ class DefaultConfig extends Config (
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case FastMulDiv => true
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case XLen => 64
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case UseFPU => {
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val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
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val env = if(site(UseVM)) List("p","v") else List("p")
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if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
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else TestGeneration.addSuites(env.map(rv64ufNoDiv))
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true
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@ -189,9 +196,9 @@ class DefaultConfig extends Config (
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case CoreInstBits => 32
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case CoreDataBits => site(XLen)
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case NCustomMRWCSRs => 0
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case ResetVector => BigInt(0x0)
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case MtvecInit => BigInt(0x8)
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case MtvecWritable => false
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case ResetVector => BigInt(0x1000)
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case MtvecInit => BigInt(0x1010)
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case MtvecWritable => true
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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@ -93,6 +93,27 @@ object TopUtils {
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conv.io.tl <> tl
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TopUtils.connectNasti(nasti, conv.io.nasti)
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}
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def makeBootROM()(implicit p: Parameters) = {
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val rom = java.nio.ByteBuffer.allocate(32)
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rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
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// for now, have the reset vector jump straight to memory
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val addrHashMap = new AddrHashMap(p(GlobalAddrMap))
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val resetToMemDist = addrHashMap("mem").start - p(ResetVector)
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require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
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val configStringAddr = p(ResetVector).toInt + rom.capacity
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rom.putInt(0x00000297 + resetToMemDist.toInt) // auipc t0, &mem - &here
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rom.putInt(0x00028067) // jr t0
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rom.putInt(0) // reserved
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rom.putInt(configStringAddr) // pointer to config string
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rom.putInt(0) // default trap vector
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rom.putInt(0) // ...
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rom.putInt(0) // ...
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rom.putInt(0) // ...
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rom.array() ++ p(ConfigString).toSeq
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}
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}
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/** Top-level module for the chip */
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@ -165,8 +186,6 @@ class Uncore(implicit val p: Parameters) extends Module
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val addrHashMap = new AddrHashMap(addrMap)
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val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
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scrFile.io.smi <> htif.io.scr
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scrFile.io.scr.attach(Wire(init = UInt(nTiles)), "N_CORES")
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scrFile.io.scr.attach(Wire(init = UInt(addrHashMap("io:int:configstring").start >> 20)), "MMIO_BASE")
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// scrFile.io.scr <> (... your SCR connections ...)
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buildMMIONetwork(p.alterPartial({case TLId => "MMIO_Outermost"}))
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@ -195,9 +214,9 @@ class Uncore(implicit val p: Parameters) extends Module
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rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port)
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io.timerIRQs := rtc.io.irqs
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val deviceTree = Module(new ROMSlave(p(ConfigString).toSeq))
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val deviceTreeAddr = ioAddrHashMap("int:configstring")
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deviceTree.io <> mmioNetwork.io.out(deviceTreeAddr.port)
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val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
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val bootROMAddr = ioAddrHashMap("int:bootrom")
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bootROM.io <> mmioNetwork.io.out(bootROMAddr.port)
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TopUtils.connectTilelinkNasti(io.mmio, mmioNetwork.io.out(ioAddrHashMap("ext").port))
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}
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@ -140,7 +140,7 @@ object DefaultTestSuites {
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val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
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val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_)
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val rv32miNames = LinkedHashSet("csr", "mcsr", "wfi", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall", "timer")
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val rv32miNames = LinkedHashSet("csr", "mcsr", "wfi", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
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val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
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val rv32u = List(rv32ui, rv32um, rv32ua)
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