jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec
This commit is contained in:
Megan Wachs
Andrew Waterman
parent
449d689a4e
commit
45bd63fcc6
@ -222,8 +222,8 @@ JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0
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stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
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$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
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--run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*-debug +vcdplusfile=foo.vpd" \
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--cmd="$(OPENOCD_DIR)/bin/openocd \
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--run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*-debug +verbose +vcdplusfile=foo.vpd" \
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--cmd="$(OPENOCD_DIR)/bin/openocd -d \
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--s $(OPENOCD_DIR)/share/openocd/scripts" \
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--freedom-e300-sim \
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$(JTAG_DTM_TEST)
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@ -232,7 +232,7 @@ stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug
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stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
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$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
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--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
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--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd \
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--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd -d \
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--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
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--freedom-u500-sim \
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$(JTAG_DTM_TEST)
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@ -476,16 +476,23 @@ class DebugModule ()(implicit val p:cde.Parameters)
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val ramWrEn = Wire(Bool())
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val dbRamAddr = Wire(UInt(width=dbRamAddrWidth))
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val dbRamAddrValid = Wire(Bool())
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val dbRamRdData = Wire (UInt(width=dbRamDataWidth))
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val dbRamWrData = Wire(UInt(width=dbRamDataWidth))
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val dbRamWrEn = Wire(Bool())
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val dbRamRdEn = Wire(Bool())
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val dbRamWrEnFinal = Wire(Bool())
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val dbRamRdEnFinal = Wire(Bool())
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val sbRamAddr = Wire(UInt(width=sbRamAddrWidth))
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val sbRamAddrValid = Wire(Bool())
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val sbRamRdData = Wire (UInt(width=sbRamDataWidth))
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val sbRamWrData = Wire(UInt(width=sbRamDataWidth))
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val sbRamWrEn = Wire(Bool())
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val sbRamRdEn = Wire(Bool())
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val sbRamWrEnFinal = Wire(Bool())
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val sbRamRdEnFinal = Wire(Bool())
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val sbRomRdData = Wire(UInt(width=tlDataBits))
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val sbRomAddrOffset = log2Up(tlDataBits/8)
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@ -625,8 +632,18 @@ class DebugModule ()(implicit val p:cde.Parameters)
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// 0x40 - 0x6F Not Implemented
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dbRamAddr := dbReq.addr( dbRamAddrWidth-1 , 0)
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dbRamWrData := dbReq.data
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dbRamAddrValid := Bool(true)
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if (dbRamAddrWidth < 4){
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dbRamAddrValid := (dbReq.addr(3, dbRamAddrWidth) === UInt(0))
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}
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sbRamAddr := sbAddr(sbRamAddrWidth + sbRamAddrOffset - 1, sbRamAddrOffset)
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sbRamWrData := sbWrData
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sbRamAddrValid := Bool(true)
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// From Specification: Debug RAM is 0x400 - 0x4FF
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if ((sbRamAddrWidth + sbRamAddrOffset) < 8){
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sbRamAddrValid := (sbAddr(7, sbRamAddrWidth + sbRamAddrOffset) === UInt(0))
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}
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require (dbRamAddrWidth >= ramAddrWidth) // SB accesses less than 32 bits Not Implemented.
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val dbRamWrMask = Wire(init=Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){Fill(dbRamDataWidth, UInt(1, width=1))})
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@ -662,7 +679,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
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ramRdData := ramMem(ramAddr)
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when (ramWrEn) { ramMem(ramAddr) := ramWrData }
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ramWrEn := sbRamWrEn | dbRamWrEn
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ramWrEn := sbRamWrEnFinal | dbRamWrEnFinal
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//--------------------------------------------------------------
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// Debug Bus Access
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@ -682,9 +699,13 @@ class DebugModule ()(implicit val p:cde.Parameters)
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RAMWrData := new RAMFields().fromBits(dbReq.data)
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dbRamWrEn := Bool(false)
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dbRamWrEnFinal := Bool(false)
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CONTROLWrEn := Bool(false)
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when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
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dbRamWrEn := dbWrEn
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when (dbRamAddrValid) {
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dbRamWrEnFinal := dbWrEn
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}
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}.elsewhen (dbReq.addr === DMCONTROL) {
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CONTROLWrEn := dbWrEn
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}.otherwise {
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@ -741,9 +762,13 @@ class DebugModule ()(implicit val p:cde.Parameters)
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}
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dbRamRdEn := Bool(false)
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dbRamRdEnFinal := Bool(false)
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when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
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dbRdData := RAMRdData.asUInt
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dbRamRdEn := dbRdEn
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when (dbRamAddrValid) {
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dbRdData := RAMRdData.asUInt
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dbRamRdEnFinal := dbRdEn
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}
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}.elsewhen (dbReq.addr === DMCONTROL) {
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dbRdData := CONTROLRdData.asUInt
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}.elsewhen (dbReq.addr === DMINFO) {
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@ -850,6 +875,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
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// SB Access Write Decoder
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sbRamWrEn := Bool(false)
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sbRamWrEnFinal := Bool(false)
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SETHALTNOTWrEn := Bool(false)
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CLEARDEBINTWrEn := Bool(false)
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@ -859,6 +885,10 @@ class DebugModule ()(implicit val p:cde.Parameters)
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when (sbAddr(11, 8) === UInt(4)){ // 0x400-0x4ff is Debug RAM
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sbRamWrEn := sbWrEn
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid) {
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sbRamWrEnFinal := sbWrEn
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sbRamRdEnFinal := sbRdEn
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}
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}.elsewhen (sbAddr === SETHALTNOT){
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SETHALTNOTWrEn := sbWrEn
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}.elsewhen (sbAddr === CLEARDEBINT){
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@ -881,6 +911,10 @@ class DebugModule ()(implicit val p:cde.Parameters)
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when (sbAddr(11,8) === UInt(4)){ //0x400-0x4ff is Debug RAM
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sbRamWrEn := sbWrEn
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid){
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sbRamWrEnFinal := sbWrEn
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sbRamRdEnFinal := sbRdEn
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}
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}
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SETHALTNOTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === SETHALTNOT(sbAddrWidth-1, sbWrSelTop + 1) &&
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@ -898,11 +932,14 @@ class DebugModule ()(implicit val p:cde.Parameters)
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sbRdData := UInt(0)
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sbRamRdEn := Bool(false)
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sbRamRdEnFinal := Bool(false)
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dbRamRdEn := Bool(false)
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when (sbAddr(11, 8) === UInt(4)) { //0x400-0x4FF Debug RAM
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sbRdData := sbRamRdData
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid) {
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sbRdData := sbRamRdData
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sbRamRdEnFinal := sbRdEn
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}
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}.elsewhen (sbAddr(11,8).isOneOf(UInt(8), UInt(9))){ //0x800-0x9FF Debug ROM
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if (cfg.hasDebugRom) {
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sbRdData := sbRomRdData
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@ -32,6 +32,13 @@ module DebugTransportModuleJtag (
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parameter JTAG_PART_NUM = 16'h0E31; // E31
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parameter JTAG_MANUF_ID = 11'h489; // As Assigned by JEDEC
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// Number of cycles which must remain in IDLE
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// The software should handle even if the
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// answer is actually higher than this, or
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// the software may choose to ignore it entirely
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// and just check for busy.
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parameter DBUS_IDLE_CYCLES = 3'h5;
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localparam IR_BITS = 5;
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localparam DEBUG_VERSION = 0;
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@ -78,7 +85,6 @@ module DebugTransportModuleJtag (
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input jtag_TMS;
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input jtag_TRST;
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// To allow tri-state outside of this block.
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output reg jtag_DRV_TDO;
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@ -110,10 +116,12 @@ module DebugTransportModuleJtag (
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reg doDbusReadReg;
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reg busyReg;
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reg stickyBusyReg;
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reg stickyNonzeroRespReg;
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reg skipOpReg; // Skip op because we're busy.
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reg downgradeOpReg; // Downgrade op because prev. op failed.
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wire busy;
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wire nonzeroResp;
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@ -128,14 +136,30 @@ module DebugTransportModuleJtag (
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wire [3:0] debugAddrBits = DEBUG_ADDR_BITS[3:0];
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wire [3:0] debugVersion = DEBUG_VERSION[3:0];
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assign dtminfo = {24'b0, debugAddrBits, debugVersion};
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wire [1:0] dbusStatus;
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wire [2:0] dbusIdleCycles;
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wire dbusReset;
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assign dbusIdleCycles = DBUS_IDLE_CYCLES;
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assign dbusStatus = {stickyNonzeroRespReg, stickyNonzeroRespReg | stickyBusyReg};
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assign dbusReset = shiftReg[16];
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assign dtminfo = {15'b0,
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1'b0, // dbusreset goes here but is write-only
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3'b0,
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dbusIdleCycles,
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dbusStatus,
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debugAddrBits,
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debugVersion};
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//busy, dtm_resp* is only valid during CAPTURE_DR,
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// so these signals should only be used at that time.
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// This assumes there is only one transaction in flight at a time.
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assign busy = busyReg & ~dtm_resp_valid;
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assign busy = (busyReg & ~dtm_resp_valid); // | stickyBusyReg;
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// This is needed especially for the first request.
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assign nonzeroResp = dtm_resp_valid ? |{dtm_resp_bits[DEBUG_OP_BITS-1:0]} : 1'b0;
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assign nonzeroResp = (dtm_resp_valid ? |{dtm_resp_bits[DEBUG_OP_BITS-1:0]} : 1'b0);
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//stickyNonzeroRespReg;
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// Interface to DM.
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// Note that this means dtm_resp_bits must only be used during CAPTURE_DR.
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@ -241,17 +265,30 @@ module DebugTransportModuleJtag (
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if (jtag_TRST) begin
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skipOpReg <= 1'b0;
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downgradeOpReg <= 1'b0;
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stickyBusyReg <= 1'b0;
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stickyNonzeroRespReg <= 1'b0;
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end else if (irReg == REG_DEBUG_ACCESS) begin
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case(jtagStateReg)
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CAPTURE_DR: begin
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skipOpReg <= busy;
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downgradeOpReg <= (~busy & nonzeroResp);
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stickyBusyReg <= busy;
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stickyNonzeroRespReg <= nonzeroResp;
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end
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UPDATE_DR: begin
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skipOpReg <= 1'b0;
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downgradeOpReg <= 1'b0;
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end
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endcase // case (jtagStateReg)
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end else if (irReg == REG_DTM_INFO) begin
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case(jtagStateReg)
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UPDATE_DR: begin
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if (dbusReset) begin
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stickyNonzeroRespReg <= 1'b0;
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stickyBusyReg <= 1'b0;
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end
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end
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endcase // case (jtagStateReg)
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end
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end // always @ (posedge jtag_TCK or posedge jtag_TRST)
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