jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec
This commit is contained in:
Megan Wachs
committed by
Andrew Waterman
Andrew Waterman
parent
449d689a4e
commit
45bd63fcc6
@ -476,16 +476,23 @@ class DebugModule ()(implicit val p:cde.Parameters)
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val ramWrEn = Wire(Bool())
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val dbRamAddr = Wire(UInt(width=dbRamAddrWidth))
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val dbRamAddrValid = Wire(Bool())
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val dbRamRdData = Wire (UInt(width=dbRamDataWidth))
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val dbRamWrData = Wire(UInt(width=dbRamDataWidth))
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val dbRamWrEn = Wire(Bool())
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val dbRamRdEn = Wire(Bool())
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val dbRamWrEnFinal = Wire(Bool())
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val dbRamRdEnFinal = Wire(Bool())
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val sbRamAddr = Wire(UInt(width=sbRamAddrWidth))
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val sbRamAddrValid = Wire(Bool())
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val sbRamRdData = Wire (UInt(width=sbRamDataWidth))
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val sbRamWrData = Wire(UInt(width=sbRamDataWidth))
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val sbRamWrEn = Wire(Bool())
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val sbRamRdEn = Wire(Bool())
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val sbRamWrEnFinal = Wire(Bool())
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val sbRamRdEnFinal = Wire(Bool())
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val sbRomRdData = Wire(UInt(width=tlDataBits))
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val sbRomAddrOffset = log2Up(tlDataBits/8)
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@ -625,8 +632,18 @@ class DebugModule ()(implicit val p:cde.Parameters)
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// 0x40 - 0x6F Not Implemented
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dbRamAddr := dbReq.addr( dbRamAddrWidth-1 , 0)
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dbRamWrData := dbReq.data
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dbRamAddrValid := Bool(true)
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if (dbRamAddrWidth < 4){
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dbRamAddrValid := (dbReq.addr(3, dbRamAddrWidth) === UInt(0))
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}
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sbRamAddr := sbAddr(sbRamAddrWidth + sbRamAddrOffset - 1, sbRamAddrOffset)
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sbRamWrData := sbWrData
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sbRamAddrValid := Bool(true)
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// From Specification: Debug RAM is 0x400 - 0x4FF
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if ((sbRamAddrWidth + sbRamAddrOffset) < 8){
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sbRamAddrValid := (sbAddr(7, sbRamAddrWidth + sbRamAddrOffset) === UInt(0))
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}
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require (dbRamAddrWidth >= ramAddrWidth) // SB accesses less than 32 bits Not Implemented.
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val dbRamWrMask = Wire(init=Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){Fill(dbRamDataWidth, UInt(1, width=1))})
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@ -662,7 +679,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
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ramRdData := ramMem(ramAddr)
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when (ramWrEn) { ramMem(ramAddr) := ramWrData }
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ramWrEn := sbRamWrEn | dbRamWrEn
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ramWrEn := sbRamWrEnFinal | dbRamWrEnFinal
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//--------------------------------------------------------------
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// Debug Bus Access
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@ -681,11 +698,15 @@ class DebugModule ()(implicit val p:cde.Parameters)
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CONTROLWrData := new CONTROLFields().fromBits(dbReq.data)
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RAMWrData := new RAMFields().fromBits(dbReq.data)
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dbRamWrEn := Bool(false)
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CONTROLWrEn := Bool(false)
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when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
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dbRamWrEn := Bool(false)
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dbRamWrEnFinal := Bool(false)
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CONTROLWrEn := Bool(false)
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when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
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dbRamWrEn := dbWrEn
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}.elsewhen (dbReq.addr === DMCONTROL) {
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when (dbRamAddrValid) {
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dbRamWrEnFinal := dbWrEn
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}
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}.elsewhen (dbReq.addr === DMCONTROL) {
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CONTROLWrEn := dbWrEn
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}.otherwise {
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//Other registers/RAM are Not Implemented.
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@ -740,10 +761,14 @@ class DebugModule ()(implicit val p:cde.Parameters)
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}
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}
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dbRamRdEn := Bool(false)
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when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
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dbRdData := RAMRdData.asUInt
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dbRamRdEn := Bool(false)
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dbRamRdEnFinal := Bool(false)
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when ((dbReq.addr >> 4) === Bits(0)) { // 0x00 - 0x0F Debug RAM
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dbRamRdEn := dbRdEn
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when (dbRamAddrValid) {
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dbRdData := RAMRdData.asUInt
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dbRamRdEnFinal := dbRdEn
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}
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}.elsewhen (dbReq.addr === DMCONTROL) {
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dbRdData := CONTROLRdData.asUInt
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}.elsewhen (dbReq.addr === DMINFO) {
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@ -850,6 +875,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
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// SB Access Write Decoder
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sbRamWrEn := Bool(false)
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sbRamWrEnFinal := Bool(false)
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SETHALTNOTWrEn := Bool(false)
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CLEARDEBINTWrEn := Bool(false)
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@ -859,6 +885,10 @@ class DebugModule ()(implicit val p:cde.Parameters)
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when (sbAddr(11, 8) === UInt(4)){ // 0x400-0x4ff is Debug RAM
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sbRamWrEn := sbWrEn
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid) {
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sbRamWrEnFinal := sbWrEn
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sbRamRdEnFinal := sbRdEn
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}
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}.elsewhen (sbAddr === SETHALTNOT){
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SETHALTNOTWrEn := sbWrEn
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}.elsewhen (sbAddr === CLEARDEBINT){
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@ -881,6 +911,10 @@ class DebugModule ()(implicit val p:cde.Parameters)
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when (sbAddr(11,8) === UInt(4)){ //0x400-0x4ff is Debug RAM
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sbRamWrEn := sbWrEn
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid){
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sbRamWrEnFinal := sbWrEn
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sbRamRdEnFinal := sbRdEn
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}
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}
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SETHALTNOTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === SETHALTNOT(sbAddrWidth-1, sbWrSelTop + 1) &&
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@ -897,12 +931,15 @@ class DebugModule ()(implicit val p:cde.Parameters)
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// SB Access Read Mux
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sbRdData := UInt(0)
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sbRamRdEn := Bool(false)
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sbRamRdEn := Bool(false)
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sbRamRdEnFinal := Bool(false)
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dbRamRdEn := Bool(false)
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when (sbAddr(11, 8) === UInt(4)) { //0x400-0x4FF Debug RAM
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sbRdData := sbRamRdData
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sbRamRdEn := sbRdEn
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when (sbRamAddrValid) {
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sbRdData := sbRamRdData
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sbRamRdEnFinal := sbRdEn
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}
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}.elsewhen (sbAddr(11,8).isOneOf(UInt(8), UInt(9))){ //0x800-0x9FF Debug ROM
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if (cfg.hasDebugRom) {
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sbRdData := sbRomRdData
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