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jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec

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This commit is contained in:
Megan Wachs
2016-09-27 10:48:04 -07:00
committed by Andrew Waterman
parent 449d689a4e
commit 45bd63fcc6
3 changed files with 102 additions and 28 deletions
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6
regression/Makefile
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@ -222,8 +222,8 @@ JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0
stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
--run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*-debug +vcdplusfile=foo.vpd" \
--cmd="$(OPENOCD_DIR)/bin/openocd \
--run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*-debug +verbose +vcdplusfile=foo.vpd" \
--cmd="$(OPENOCD_DIR)/bin/openocd -d \
--s $(OPENOCD_DIR)/share/openocd/scripts" \
--freedom-e300-sim \
$(JTAG_DTM_TEST)
@ -232,7 +232,7 @@ stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug
stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd \
--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd -d \
--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
--freedom-u500-sim \
$(JTAG_DTM_TEST)