From 6be569be9f40f286fd9e97fb46019020fdee9aa1 Mon Sep 17 00:00:00 2001 From: Ben Keller Date: Wed, 7 Sep 2016 15:27:26 -0700 Subject: [PATCH] Turn on the inferRW Firrtl pass Without this, all of the memories wind up as two-ported. --- vsim/Makefrag-verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index 349b1e3b..9cab4cc9 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -11,7 +11,7 @@ $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir) $(generated_dir)/%.v $(generated_dir)/%.conf : $(generated_dir)/%.fir $(FIRRTL_JAR) mkdir -p $(dir $@) - $(FIRRTL) -i $< -o $@ -X verilog --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf + $(FIRRTL) -i $< -o $@ -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(MODEL).$(CONFIG).conf $(generated_dir)/$(MODEL).$(CONFIG).behav_srams.v : $(generated_dir)/$(MODEL).$(CONFIG).conf $(mem_gen) cd $(generated_dir) && \