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Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"

This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
This commit is contained in:
Henry Cook 2017-10-05 00:26:44 -07:00
parent 5a84564203
commit 45581e60f0
5 changed files with 3 additions and 25 deletions

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@ -3,7 +3,6 @@
package freechips.rocketchip.coreplex
import Chisel._
import chisel3.experimental.dontTouch
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
@ -115,9 +114,9 @@ trait HasRocketTilesModuleImp extends LazyModuleImp
require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
vectors.head.getWidth
}
val rocket_tile_inputs = dontTouch(Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
})))) // dontTouch keeps constant prop from sucking these signals into the tile
})))
// Unconditionally wire up the non-diplomatic tile inputs
outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) =>
@ -131,7 +130,7 @@ trait HasRocketTilesModuleImp extends LazyModuleImp
rocket_tile_inputs.zipWithIndex.foreach { case(wire, i) =>
wire.clock := clock
wire.reset := reset
wire.hartid := i.U
wire.hartid := UInt(i)
wire.reset_vector := global_reset_vector
}
}

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@ -4,7 +4,6 @@
package freechips.rocketchip.rocket
import Chisel._
import chisel3.experimental.dontTouch
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.coreplex._
import freechips.rocketchip.diplomacy._
@ -185,7 +184,6 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
implicit val edge = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new HellaCacheBundle(outer))
dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable)
fifoManagers.foreach { m =>

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@ -6,7 +6,6 @@ import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
/** Example Top with periphery devices and ports, and a Rocket coreplex */
class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
@ -26,4 +25,3 @@ class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends Ro
with HasMasterAXI4MMIOPortModuleImp
with HasSlaveAXI4PortModuleImp
with HasPeripheryBootROMModuleImp
with DontTouch

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@ -14,7 +14,6 @@ class TestHarness()(implicit p: Parameters) extends Module {
val dut = Module(LazyModule(new ExampleRocketSystem).module)
dut.reset := reset | dut.debug.ndreset
dut.dontTouchPorts()
dut.tieOffInterrupts()
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()

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@ -4,7 +4,6 @@
package freechips.rocketchip.util
import Chisel._
import chisel3.experimental.{dontTouch, RawModule}
import freechips.rocketchip.config.Parameters
import scala.math._
@ -22,21 +21,6 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle {
}
}
// TODO: replace this with an implicit class when @chisel unprotects dontTouchPorts
trait DontTouch {
self: RawModule =>
/** Marks every port as don't touch
*
* @note This method can only be called after the Module has been fully constructed
* (after Module(...))
*/
def dontTouchPorts(): this.type = {
self.getModulePorts.foreach(dontTouch(_))
self
}
}
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()